John Wesley Leon

US Patent:

8074082, Dec 6, 2011

Filed:

Oct 11, 2005

Appl. No.:

11/248659

Inventors:

Volkan H. Ozguz - Aliso Viejo CA, US
John Leon - Anaheim CA, US

Assignee:

Aprolase Development Co., LLC - Wilmington DE

International Classification:

G06F 11/30
G06F 1/26

US Classification:

713194, 726 34, 726 35, 380 29, 380264

Abstract:

An anti-tamper module is provided for protecting the contents and functionality of an integrated circuit incorporated in the module. The anti-tamper module is arranged in a stacked configuration having multiple layers. A connection layer is provided for connecting the module to an external system. A configurable logic device is provided for routing connections between the integrated circuit and the connection layer. Specifically, the configurable logic device is programmable to create logical circuits connecting at least one of the input/output connectors of the integrated circuit to at least one of the input/output connectors of the connection layer. Configuration information for programming the reconfigurable logic device is stored in a memory within the module.

US Patent:

8519739, Aug 27, 2013

Filed:

May 2, 2011

Appl. No.:

13/098655

Inventors:

John Leon - Anaheim CA, US

Assignee:

ISC8 Inc. - Costa Mesa CA

International Classification:

H03K 19/173

US Classification:

326 38

Abstract:

A high-speed processor core having a plurality of individual FPGA-based processing elements configured in a synchronous or asynchronous pipeline architecture with direct processor-to-memory interconnectivity that avoids the latency and bus contention delays of FPGAs using conventional bused memory. The high-speed processor core has one or more memory structures such as SDRAM or QDR electronic memory and is electrically coupled directly to one or more FPGAs using an access lead network to provide a pipelined set of FPGA-based processor elements for processing one or more predetermined operations such as one or more detection algorithms at line rates.

US Patent:

20110031982, Feb 10, 2011

Filed:

Aug 4, 2010

Appl. No.:

12/806127

Inventors:

John Leon - Anaheim Hills CA, US
James Yamaguchi - Laguna Niguel CA, US
Volkan Ozguz - Aliso Viejo CA, US
W. Eric Boyd - Irvine CA, US

Assignee:

Irvine Sensors Corporation - Costa Mesa CA

International Classification:

G01R 27/28
H02H 3/08
H05K 7/00

US Classification:

324649, 361 931, 361783

Abstract:

A device and method are disclosed comprising one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package (such as a TSOP, BGA or other prepackaged IC) a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs.In one embodiment, the electrically conductive nano-structure is in electrical connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the electrically conductive nano-structure is breached or altered. The device may be configured to blow one or more fuses or overcurrent protection devices when the electrically conductive nano-structure is breached or altered.In a further embodiment, one or more electrically conductive nano-structures are used to interconnect and reroute one or more electrical connections between one or more ICs (or dummy leads and vias) to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device, i.e., a set of connections that cannot be observed by standard test means such as by X-ray or conventional microscope.

US Patent:

20110227603, Sep 22, 2011

Filed:

Mar 11, 2011

Appl. No.:

13/045880

Inventors:

John Leon - Anaheim CA, US
James Yamaguchi - Laguna Niguel CA, US
W. Eric Boyd - La Mesa CA, US
Volkan Ozguz - Aliso Viejo CA, US

Assignee:

Irvine Sensors Corporation - Costa Mesa CA

International Classification:

H03K 19/00
H02H 3/08
G01R 27/26
G01R 27/08

US Classification:

326 8, 361 87, 324654, 324658, 324691, 324649

Abstract:

A device and method using one or more electrically conductive nano-structures defined on one or more surfaces of a microelectronic circuit such as an integrated circuit die, microelectronic circuit package a stacked microelectronic circuit package, or on the surface of one or more layers in a stack of layers containing one or more ICs. The nano-structure is in connection with a monitoring circuit and acts as a “trip wire” to detect unauthorized tampering with the device or module. Such a monitoring circuit may include a power source such as an in-circuit or in-module battery and a “zeroization” circuit within the chip or package to erase the contents of a memory when the nano-structure is breached or altered. One or more electrically conductive nano-structures interconnect and reroute one or more electrical connections between one or more ICs to create an “invisible” set of electrical connections on the chip or stack to obfuscate an attempt to reverse engineer the device. microscope.

US Patent:

20110267190, Nov 3, 2011

Filed:

May 2, 2011

Appl. No.:

13/098738

Inventors:

Ellwood Payson - Fullerton CA, US
John Leon - Anaheim CA, US

Assignee:

Irvine Sensors Corporation - Costa Mesa CA

International Classification:

G08B 1/08

US Classification:

34053931

Abstract:

An anti-tampering device and method to inhibit or prevent unauthorized probing of an electronic circuit. Propriety target circuitry transmits a distinct signature in the form of an RF signal which is received by the RF anti-tampering detection circuitry. The transmitted RF signature is monitored by the RF anti-tampering detection circuitry for user-defined changes. In the event an unauthorized attempt is made to probe the target system electronics, the mass of the probe alters the RF transmission characteristics of the RF transmission media, changing the RF signature. The altered RF signature is received by the receiving antenna and RF receiver and is processed by signal processing electronics. The change in the RF signature indicates a tamper event and a predefined anti-tamper event is generated.

US Patent:

20120185636, Jul 19, 2012

Filed:

Feb 1, 2012

Appl. No.:

13/363571

Inventors:

John Leon - Anaheim CA, US
W. Eric Boyd - La Mesa CA, US
Sambo He - Riverside CA, US
Christian Krutzik - Costa Mesa CA, US

Assignee:

ISC8, Inc. - Costa Mesa CA

International Classification:

G06F 12/00
G06F 12/02

US Classification:

711102, 711154, 711E12001, 711E12008

Abstract:

A high capacity, secure and tamper-resistant computer data memory device. The device uses a plurality of dedicated memory controller elements in communication with an anti-tamper module that generates a tamper response when a predetermined tamper event occurs. The tamper response may be provided as the erasure or zeroization of the contents of a memory in the devices such as erasing one or more encryption keys. The elements of the device are preferably provided in a stacked configuration with rerouted I/O pads to obfuscate the I/O and function of the devices in the stack. In one embodiment, a data transfer governance means is provided. In a further embodiment, a current negotiation means is disclosed to permit the device to request a predetermined current from a host device. In a yet further embodiment, a portable safe house computing device is provided.

US Patent:

20220263800, Aug 18, 2022

Filed:

Dec 23, 2021

Appl. No.:

17/561003

Inventors:

- Reston VA, US
John Leon - Glendale CA, US

International Classification:

H04L 9/40

Abstract:

A plurality of system nodes coupled via a dedicated private network is described herein. The nodes offer an end-to-end solution for protecting against network-based attacks. The nodes can include network gateways that allow remote systems, such as servers located at an entity's place of operation or a data center accessible by the entity, to securely transmit data between the nodes and the remote systems. For example, the network gateways can transmit split data into different portions, and transmit each portion over a different path through a public network to mitigate the effects of man-in-the-middle attacks. Once data reaches a node, transmission of the data from one node to another can pass through multiple intermediary nodes via the dedicated private network. The nodes and/or remote systems may also include cross-domain guard devices that control whether data can pass from one security domain to another.

US Patent:

20200412733, Dec 31, 2020

Filed:

Sep 14, 2020

Appl. No.:

17/020616

Inventors:

- Reston VA, US
John Leon - Glendale CA, US

International Classification:

H04L 29/06
G06F 9/445
G06F 21/62

Abstract:

A plurality of system nodes coupled via a dedicated private network is described herein. The nodes offer an end-to-end solution for protecting against network-based attacks. The nodes can also execute applications locally at the request of a user device such that a user operating the user device can use the applications executed locally on the nodes as if the applications were executing locally on the user device. To protect user data, the nodes may not transmit any user data to the user device. Rather, a node can generate a graphical representation of the environment in which the applications are executed, and transmit the graphical representation to the user device. As the user performs actions that result in a change of a graphical view of the environment in which the applications are executed, the node can generate and transmit new graphical representations of the environment to the user device.