John L Lin

US Patent:

6815276, Nov 9, 2004

Filed:

Oct 3, 2002

Appl. No.:

10/264038

Inventors:

Philip L. Hower - Concord MA
John Lin - Chelmsford MA
Sameer P. Pendharkar - Richardson TX
Steven L. Merchant - Bedford NH

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21336

US Classification:

438197, 438294

Abstract:

Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.

US Patent:

6878999, Apr 12, 2005

Filed:

Jul 15, 2003

Appl. No.:

10/619699

Inventors:

Philip L. Hower - Concord MA, US
John Lin - Chelmsford MA, US
Sameer Pendharkar - Richardson TX, US
Steven L. Jensen - Amherst NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L029/76
H01L029/94
H01L031/062
H01L031/113
H01L031/119

US Classification:

257343, 257335, 257341

Abstract:

Segmented transistor devices are provided, wherein contiguous individual transistor segments extend along corresponding segment axes, in which two or more of the segment axes are at a non-zero angle with respect to one another. The segmentation of the transistor provides a high overall device aspect ratio which may be easily fit into pre-existing circuit blocks or cells in a device layout, thereby facilitating device scaling.

US Patent:

6900101, May 31, 2005

Filed:

Jun 13, 2003

Appl. No.:

10/461214

Inventors:

John Lin - Chelmsford MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L021/8236

US Classification:

438276, 438227, 438297, 438306, 438519, 438524, 257E21417

Abstract:

LDMOS transistor devices and fabrication methods are provided, in which additional dopants are provided to region of a substrate near a thick dielectric between the channel and the drain to reduce device resistance without significantly impacting breakdown voltage. The extra dopants are added by implantation prior to formation of the thick dielectric, such as before oxidizing silicon in a LOCOS process or following trench formation and before filling the trench in an STI process.

US Patent:

7141455, Nov 28, 2006

Filed:

Nov 12, 2003

Appl. No.:

10/712455

Inventors:

Binghua Hu - Plano TX, US
Howard S. Lee - Plano TX, US
Henry L. Edwards - Garland TX, US
John Lin - Chelmsford MA, US
Vladimir N. Bolkhovsky - Framingham MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/332

US Classification:

438135, 438306, 438305

Abstract:

A double diffused region (), (), () is formed in an epitaxial layer (). The double diffused region is formed by first implanting light implant specie such as boron through an opening in a photoresist layer prior to a hard bake process. Subsequent to a hard bake process heavy implant specie such as arsenic can be implanted into the epitaxial layer. During subsequent processing such as LOCOS formation the double diffused region is formed. A dielectric layer () is formed on the epitaxial layer () and gate structures (), () are formed over the dielectric layer ().

US Patent:

7187034, Mar 6, 2007

Filed:

Jul 9, 2004

Appl. No.:

10/888776

Inventors:

Philip L. Hower - Concord MA, US
John Lin - Chelmsford MA, US
Sameer P. Pendharkar - Richardson TX, US
Steven L. Merchant - Bedford NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/78

US Classification:

257341, 257401, 257E2912, 257E29256

Abstract:

Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.

US Patent:

7195965, Mar 27, 2007

Filed:

Nov 22, 2002

Appl. No.:

10/302256

Inventors:

John Lin - Chelmsford MA, US
Philip L. Hower - Concord MA, US
Taylor R. Efland - Richardson TX, US
Sameer Pendharkar - Richardson TX, US
Vladimir Bolkhovsky - Framingham MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/8248

US Classification:

438202, 438309

Abstract:

The concept of the present invention describes a semiconductor device with a junction between a lightly doped region and a heavily doped region , wherein the junction has an elongated portion and curved portions. The doping concentration of the lightly doped region is configured so that it exhibits higher resistivity in the proximity of the curved portion by an amount suitable to lower the electric field strength during device operation and thus to offset the increased field strength caused by the curved portion. As a consequence, the device breakdown voltage in the curved junction portion becomes equal to or greater than the breakdown voltage in the linear portion.

US Patent:

7345343, Mar 18, 2008

Filed:

Aug 2, 2005

Appl. No.:

11/195283

Inventors:

Tony T. Phan - Flower Mound TX, US
William C. Loftin - Plano TX, US
John Lin - Chelmsford MA, US
Philip L. Hower - Concord MA, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/84

US Classification:

257347, 438149

Abstract:

The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (), in one embodiment without limitation, includes a dielectric layer () located over a wafer substrate (), and a semiconductor substrate () located over the dielectric layer (), the semiconductor substrate () having one or more transistor devices () located therein or thereon. The integrated circuit () may further include an interconnect () extending entirely through the semiconductor substrate () and the dielectric layer (), thereby electrically contacting the wafer substrate ().

US Patent:

7417270, Aug 26, 2008

Filed:

Jun 23, 2004

Appl. No.:

10/874479

Inventors:

Philip L. Hower - Concord MA, US
David A. Walch - Bedford NH, US
John Lin - Chelmsford MA, US
Steven L. Merchant - Bedford NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/80

US Classification:

257270, 257269, 257285, 257286, 257E27012

Abstract:

A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.