John C Lovelace

US Patent:

7036007, Apr 25, 2006

Filed:

Sep 9, 2002

Appl. No.:

10/237349

Inventors:

Todd A. Schelling - Irmo SC, US
Amy L. O'Donnell - Ann Arbor MI, US
Craig M. Valine - Windsor CO, US
William R. Greene - Fort Collins CO, US
Bassam N. Elkhoury - Olympia WA, US
John V. Lovelace - Irmo SC, US
David J. O'Shea - Costa Mesa CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15/177
G06F 9/00
G06F 9/24

US Classification:

713 1, 713 2, 713100

Abstract:

One embodiment of the invention provides a firmware architecture which splits firmware modules to support safe updates of specific modules as well as supporting multiple different processors. A firmware image is partitioned into several different binaries based on their update requirements and processor/platform dependence. A firmware interface table enables safe updates by enabling the option of redundant copies of specific modules as well as supporting systems with different and/or multiple processor types, mixed processors from the same family, and/or fault resilient firmware updates.

US Patent:

7107405, Sep 12, 2006

Filed:

May 30, 2003

Appl. No.:

10/449244

Inventors:

John V. Lovelace - Irmo SC, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00

US Classification:

711133, 711135, 711143, 711144, 711113

Abstract:

In one embodiment of the present invention, a method includes storing system management mode data in a cache of a system during a system management mode; and preventing the system from leaving the system management mode until the system management mode data is evicted from the cache.

US Patent:

20180181504, Jun 28, 2018

Filed:

Dec 23, 2016

Appl. No.:

15/389462

Inventors:

- Santa Clara CA, US
John Van Lovelace - Irmo SC, US
Christopher Mozak - Beaverton OR, US
Bill Nale - Livemore CA, US

International Classification:

G06F 13/16
G06F 3/06
G11C 11/4076
G11C 11/4093

Abstract:

The present disclosure relates to an apparatus for training one or more signal timing relations of a control interface between a registering clock driver and one or more data buffers of a memory module comprising a plurality of memory chips, the control interface comprising a clock signal and at least one control signal. The apparatus includes control circuitry which is configured to adjust a relative timing between the at least one control signal and the clock signal based on samples of the at least one control signal sampled based on the clock signal

US Patent:

20180095889, Apr 5, 2018

Filed:

Oct 1, 2016

Appl. No.:

15/283318

Inventors:

- Santa Clara CA, US
Wenjuan Mao - Shanghai, CN
Qiang Li - Shanghai, CN
John V. Lovelace - Irmo SC, US
James R. Goffena - Columbia SC, US

International Classification:

G06F 12/0895
G06F 12/0875
G06F 12/10
G06F 9/445

Abstract:

Technologies for control and status register (CSR) access include a computing device that starts a firmware initialization phase. The firmware accesses a CSR at an abstract CSR address. The computing device determines whether an upper part of the CSR address matches a cached upper part of a previously accessed CSR address. If the upper parts do not match, the computing device converts the CSR address into a physical address and caches the upper part of the CSR address and the upper part of the physical address. If the upper parts match, the computing device combines a cached upper part of a previously accessed physical address with an offset of the CSR address. The upper part may include 20 bits and the lower part may include 12 bits. The physical address may be a PCIe address of the CSR added with an MMCFG base address. Other embodiments are described and claimed.

US Patent:

20170168747, Jun 15, 2017

Filed:

Dec 11, 2015

Appl. No.:

14/966933

Inventors:

- Santa Clara CA, US
John V. Lovelace - Irmo SC, US
Priscilla Y. Lam - Seattle WA, US
Richard P. Mangold - Forest Grove OR, US
Asher M. Altman - Bedford MA, US
Shachi K. Thakkar - Folsom CA, US

International Classification:

G06F 3/06
G06F 1/32

Abstract:

Embodiments are generally directed to intelligent memory support for platform reset operation. An embodiment of a memory module includes a memory module controller and one or more memory banks. The memory module controller is to perform one or more internal reset processes as required for the memory module, and is to support a plurality of host platform reset processes to synchronize with the host platform.

US Patent:

20160232962, Aug 11, 2016

Filed:

Mar 31, 2016

Appl. No.:

15/087963

Inventors:

- Santa Clara CA, US
Kevin B. Moore - Chapin SC, US
John V. Lovelace - Irmo SC, US
Theodore Z. Schoenborn - Portland OR, US
Bryan L. Spry - Portland OR, US
Christopher E. Yunker - Beaverton OR, US

International Classification:

G11C 11/4091
G11C 11/4093
G11C 11/4099

Abstract:

Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

US Patent:

20160098366, Apr 7, 2016

Filed:

Dec 11, 2015

Appl. No.:

14/967226

Inventors:

- Santa Clara CA, US
John V. LOVELACE - Irmo SC, US
Murugasamy M. NACHIMUTHU - Beaverton OR, US
Tuan M. QUACH - Fullerton CA, US

International Classification:

G06F 13/16
G06F 13/42
G06F 12/02

Abstract:

Provided are a method and apparatus for method and apparatus for encoding registers in a memory module. A mode register command is sent to the memory module over a bus, initialization of the memory module before the bus to the memory module is trained for bus operations, to program one of a plurality of mode registers in the memory module, wherein the mode register command indicates one of the mode registers and includes data for the indicated mode register

US Patent:

20140211579, Jul 31, 2014

Filed:

Dec 23, 2013

Appl. No.:

14/139558

Inventors:

John V. Lovelace - Irmo SC, US

International Classification:

G11C 11/406
G11C 29/04

US Classification:

365200

Abstract:

Techniques and mechanisms to dynamically adjustment a timing of commands to access a dynamic random access memory (DRAM). In an embodiment, a memory controller monitors an error rate of the DRAM and, based on such monitoring, identifies that the error rate is within a predetermined range. In response to the error rate being within the predetermined range, one or more signals are generated to dynamically modify a command timing setting. In another embodiment, modification of the command timing setting is to transition a memory controller from sending memory refresh commands successively at one rate to sending memory refresh commands successively at a different rate.