John B Lovelace

US Patent:

20220300197, Sep 22, 2022

Filed:

May 20, 2022

Appl. No.:

17/749916

Inventors:

- Santa Clara CA, US
Tonia M. ROSE - Wendell NC, US
George VERGIS - Portland OR, US
John V. LOVELACE - Driftwood TX, US

International Classification:

G06F 3/06

Abstract:

Autonomous QCS and QCA training by the RCD can remove host intervention, freeing the host to handle other tasks while the RCD trains the backside CS and CA buses. In one example, the RCD autonomously trains QCS and/or QCA signal lines by triggering the DRAMs entry into a training mode, driving the signal lines with patterns, and sweeping through delay values for the signal lines. The RCD receives training feedback from the DRAMs over a sideband bus (such as an I3C bus) and programs a delay for the one or more signal lines based on the training feedback. Thus, autonomous QCS and QCA training can reduce training time for every boot by removing host intervention and saving hose cycles.

US Patent:

20220301608, Sep 22, 2022

Filed:

Jun 1, 2022

Appl. No.:

17/830118

Inventors:

- Santa Clara CA, US
Tonia M. ROSE - Wendell NC, US
George VERGIS - Portland OR, US
John V. LOVELACE - Driftwood TX, US

International Classification:

G11C 7/22
G11C 7/10
G11C 8/18

Abstract:

An apparatus is described. The apparatus includes a register clock redriver (RCD) chip comprising a buffer communication (BCOM) interface, a BCOM training control circuit and BCOM training control register space, the BCOM training control circuit is to: transmit a series of symbol transmissions over the BCOM interface to a data buffer with different respective clock phase delays to sweep the symbol transmissions within an eye window; collect resultants of the symbol transmissions from the data buffer; and, perform an analysis on the resultants to determine an appropriate clock phase within the eye window.

US Patent:

20230125412, Apr 27, 2023

Filed:

Dec 21, 2022

Appl. No.:

18/086639

Inventors:

- Santa Clara CA, US
Tonia M. ROSE - Wendell NC, US
John V. LOVELACE - Driftwood TX, US
George VERGIS - Portland OR, US

International Classification:

G11C 7/10
G11C 7/22

Abstract:

An apparatus is described. The apparatus includes a data buffer chip having write leveling training circuitry. The write leveling training circuitry to detect when a sampled value of a WL pulse within a memory chip has changed. Another apparatus is described. The other apparatus includes a registering clock driver (RCD) chip having write leveling training circuitry to determine when to send a write command to a memory chip and a data buffer chip during an external write leveling training process for the memory chip.

US Patent:

20230017161, Jan 19, 2023

Filed:

Sep 22, 2022

Appl. No.:

17/950663

Inventors:

- Santa Clara CA, US
Tonia M. ROSE - Wendell NC, US
George VERGIS - Portland OR, US
John V. LOVELACE - Driftwood TX, US

International Classification:

G11C 7/10
G11C 8/18

Abstract:

System boot time is decreased by performing Memory Receive enable (MRE) training and MDQ-MDQS Read Delay (MRD) training on a buffered Dual In-Line Memory Module (DIMM). MRE training configures the time at which a data buffer on the buffered DIMM enables its receivers to capture data read from DRAM integrated circuits on a MDQ/MDQS bus between the DRAM and the data buffer on the DIMM. After the MRE training has completed, the data buffer is configured to enable the data buffer receivers to receive data on the MDQ bus on the buffered DIMM during the preamble of the incoming MDQS burst from a read transaction in the DRAM. MRD training tunes the relationship between the MDQ/MDQS bus to ensure sufficient setup and hold eye margins for MDQ so that the data buffer optimally samples the data driven by the DRAM during reads of the DRAM.