John R Lovelace

US Patent:

20210382640, Dec 9, 2021

Filed:

Aug 25, 2021

Appl. No.:

17/411960

Inventors:

- Santa Clara CA, US
John V. LOVELACE - Driftwood TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 3/06
G06F 11/10

Abstract:

Initialization of a memory can have different phases, first initializing a portion of memory for BIOS (basic input/output system) and initializing other portions of memory while the BIOS is operating. The initialization of the memory can be performed by the error scrub engine. In a first mode of operation, the scrub engine can initialize memory locations, then transition to performing scrub operations.

US Patent:

20200065266, Feb 27, 2020

Filed:

Aug 1, 2019

Appl. No.:

16/529700

Inventors:

- Santa Clara CA, US
John V. LOVELACE - Driftwood TX, US
John R. GOLES - Folsom CA, US

International Classification:

G06F 13/16
G06F 1/10

Abstract:

A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.

US Patent:

20190095361, Mar 28, 2019

Filed:

Sep 28, 2017

Appl. No.:

15/718346

Inventors:

- Santa Clara CA, US
John V. LOVELACE - Driftwood TX, US
John R. GOLES - Folsom CA, US

International Classification:

G06F 13/16
G06F 1/10

Abstract:

A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.