John L Mauer

US Patent:

46914358, Sep 8, 1987

Filed:

May 13, 1981

Appl. No.:

6/263227

Inventors:

Narasipur G. Anantha - Hopewell Junction NY
Harsaran S. Bhatia - Wappingers Falls NY
Santosh P. Gaur - Wappingers Falls NY
John L. Mauer - South Kent CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21385

US Classification:

437175

Abstract:

A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.

US Patent:

44546475, Jun 19, 1984

Filed:

Aug 27, 1981

Appl. No.:

6/296933

Inventors:

Richard C. Joy - Beacon NY
Bernard M. Kemlage - Kingston NY
John L. Mauer - South Kent CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2176

US Classification:

29576W

Abstract:

An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions.

US Patent:

47960698, Jan 3, 1989

Filed:

Jun 18, 1987

Appl. No.:

7/063345

Inventors:

Narasipur G. Anantha - Hopewell Junction NY
Harsaran S. Bhatia - Wappingers Falls NY
Santosh P. Gaur - Wappingers Falls NY
John L. Mauer - South Kent CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2948
H01L 2934
H01L 2904

US Classification:

357 15

Abstract:

A method is disclosed for fabricating a small area, self aligned guard ring in a Schottky barrier diode. A vertically-walled hole is anisotropically etched completely through a dielectric layer on a silicon substrate. A layer of doped polycrystalline silicon is deposited over the apertured dielectric layer. The polycrystalline silicon is reactively ion etched away to leave only a lining about the perimeter of the hole in the dielectric layer. The structure is heated to diffuse the dopant from the lining into the substrate. Schottky diode metal is deposited on the substrate exposed through the lined aperture in the dielectric layer.

US Patent:

43892949, Jun 21, 1983

Filed:

Jun 30, 1981

Appl. No.:

6/279129

Inventors:

Narasipur G. Anantha - Hopewell Junction NY
Harsaran S. Bhatia - Wappingers Falls NY
John L. Mauer - South Kent CT
Homi G. Sarkary - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

C23C 1500

US Classification:

204192E

Abstract:

A method for eliminating deposited residues, for example polysilicon residue, on vertical silicon dioxide sidewalls that have been reactive ion etched includes reshaping the sidewalls to have a slope of at least +30. degree. relative to the vertical direction of the sidewall.

US Patent:

44940041, Jan 15, 1985

Filed:

Jul 1, 1983

Appl. No.:

6/510385

Inventors:

John L. Mauer - Sherman CT
Michel S. Michail - Wappingers Falls NY
Ollie C. Woodard - Poughkeepsie NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01J 37302

US Classification:

2504922

Abstract:

An electron beam method and apparatus, for writing patterns, such as on semiconductor wafers, in which the writing field is divided into a large number of overlapping subfields with a predetermined periodicity. Subfield to subfield moves are made in a stepped sequential scan, such as raster, while patterns, within a subfield, are addressed using vector scan and written using a sequential scan. Significant improvement in throughput results by the use of this electron beam method and apparatus which preferably employs magnetic deflection for the sequential scanning the subfields and electric deflection for vector scanning within the subfield.

US Patent:

52643280, Nov 23, 1993

Filed:

Apr 24, 1992

Appl. No.:

7/874286

Inventors:

Ronald A. DellaGuardia - Poughkeepsie NY
John L. Mauer - South Kent CT
David E. Seeger - Congers NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G03C 502

US Classification:

430322

Abstract:

The present invention provides a method for determining the development endpoint in a X-ray lithographic process. Endpoint is determined by visually observing resist test field patterns through a microscope during the developing step. During the developing, changing test field patterns are formed because test field locations each had been exposed simultaneously to different radiation doses. These different doses are produced when radiation passes through a mask containing a plurality of different size radiation attenuators. When the changing test field pattern matches a known pattern, which is correlated to the desired development endpoint, the workpiece is removed from the developing step.

US Patent:

46880690, Aug 18, 1987

Filed:

Dec 6, 1985

Appl. No.:

6/806060

Inventors:

Richard C. Joy - Beacon NY
Bernard M. Kemlage - Kingston NY
John L. Mauer - South Kent CT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 2972

US Classification:

357 34

Abstract:

An integrated circuit structure having substrate contacts formed as a part of the isolation structure and the method to form such structure is described. The integrated circuit structure is composed of a monocrystalline silicon body having a pattern of dielectric isolation surrounding regions of the monocrystalline silicon in the body. The dielectric isolation pattern includes a recessed dielectric portion at and just below the surface of the integrated circuit and a deep portion which extends through the recessed dielectric portion and extends further into the monocrystalline silicon body than the recessed portion. A highly doped polycrystalline silicon substrate contact is located within the deep portion of the pattern of isolation. The substrate contact extends from the surface of the pattern of isolation down to the bottom of the deep portion of the isolation where the contact electrically connects to the silicon body. Any of a variety of integrated circuit device structures may be incorporated within the monocrystalline silicon regions.

US Patent:

42227925, Sep 16, 1980

Filed:

Sep 10, 1979

Appl. No.:

6/073593

Inventors:

Reginald F. Lever - Putnam Valley NY
John L. Mauer - Sherman CT
Alwin E. Michel - Ossining NY
Laura B. Rothman - Sherman CT

Assignee:

International Business Machines Corporation - NY

International Classification:

H01L 2126
H01L 21316
H01L 2176

US Classification:

148 15

Abstract:

A planar deep oxide isolation process for providing deep wide silicon dioxide filled trenches in the planar surface of a silicon semiconductor substrate, said process comprising the steps: (a) forming deep wide trenches in the planar surface of the silicon substrate; (b) forming a thin layer of silicon dioxide on the planar surface of the silicon substrate and the exposed silicon surfaces of said deep wide trenches; (c) applying resin glass (polysiloxane) to the planar surface of said semiconductor substrate and within said deep wide trenches; (d) spinning off at least a portion of the resin glass on the planar surface of the substrate; (e) baking the substrate at a low temperature; (f) exposing the resin glass contained within the deep wide trenches of substrate to the energy of an E-beam; (g) developing the resin glass contained on said substrate in a solvent; (h) heating said substrate in oxygen to convert said resin glass contained within said deep wide trenches to silicon dioxide; (i) depositing a layer of silicon dioxide to provide a planar silicon dioxide surface on the exposed the surface of said substrate; and (j) planarize exposed silicon dioxide surface to silicon of substrate. A planar deep oxide isolation process for providing deep wide silicon dioxide filled trenches in the planar surface of a silicon semiconductor substrate as recited in the preceding paragraph, wherein the following steps are performed in lieu of step i of claim 1, said steps comprising: (i-1) apply a second thin layer of resin glass; and (i-2) convert said resin glass to silicon dioxide.