John Gilbert Merrill

US Patent:

54105510, Apr 25, 1995

Filed:

Jan 2, 1992

Appl. No.:

7/816117

Inventors:

Robert Edwards - San Jose CA
Michael G. Fisher - Mountain View CA
John Merrill - Saratoga CA
Gary Woffinden - Rexburg ID

Assignee:

Andahl Corporation - Sunnyvale CA

International Classification:

G06F 1100

US Classification:

371 251

Abstract:

To verify proper interconnection of an interconnect network, a transitory test signal is introduced at a first node of a network within a system under test. A search is made of all other system nodes for responsive transitions. A comparison is made between the addresses of nodes where transitions are observed within a predetermined time span and the addresses of nodes where transitions are expected. The predetermined time span is adjusted to detect missing or miswired line-conditioning components.

US Patent:

51229781, Jun 16, 1992

Filed:

Nov 13, 1989

Appl. No.:

7/435745

Inventors:

John F. Merrill - Saratoga CA

Assignee:

Amdahl Corporation - Sunnyvale CA

International Classification:

G01R 3128

US Classification:

364569

Abstract:

Method and apparatus are disclosed for measuring the clock pulse width as it is received at a subject latch point in a system. In the system, test data distribution means is provided for distributing a test data signal from a test data source point to the data input of the subject latch point. The subject latch point is constructed to hold on its output the signal which was on the data input at selectably either the leading or trailing edge of the clock pulse. By adjusting the presettable delay in a test data signal generator, and observing the steady state output of the subject latch point conveniently after the last clock pulse in a burst reaches the subject latch point, it is possible to determine a delay setting at which the test data signal transition and the selected edge of the last clock pulse in the burst reach the subject latch point at substantially the same time. Using this method, two measurements are taken. The first measurement is obtained with the leading edge of each clock pulse selected as the effective edge for the subject latch point, and the second measurement is obtained with the trailing edge of each clock pulse selected as the effective edge for the subject latch point.

US Patent:

43479359, Sep 7, 1982

Filed:

May 16, 1979

Appl. No.:

6/039527

Inventors:

John T. Merrill - Berkeley CA

Assignee:

The United States of America as represented by the United States
Department of Energy - Washington DC

International Classification:

B07C 5342

US Classification:

209 32

Abstract:

An improved method of sorting biological cells in a conventional cell sorter apparatus includes generating a fluid jet containing cells to be sorted, measuring the distance between the centers of adjacent droplets in a zone thereof defined at the point where the fluid jet separates into descrete droplets, setting the distance between the center of a droplet in said separation zone and the position along said fluid jet at which the cell is optically sensed for specific characteristics to be an integral multiple of said center-to-center distance, and disabling a charger from electrically charging a specific droplet if a cell is detected by the optical sensor in a position wherein it will be in the neck area between droplets during droplet formation rather than within a predetermined distance from the droplet center.

US Patent:

52355667, Aug 10, 1993

Filed:

Oct 4, 1990

Appl. No.:

7/592590

Inventors:

John F. Merrill - Saratoga CA

Assignee:

Amdahl Corporation - Sunnyvale CA

International Classification:

G04F 800
G01R 3102
G01R 1512

US Classification:

368113

Abstract:

Method and apparatus are disclosed for measuring the clock offset between a reference latch point and a subject latch point in a system. In the system, an associated latch point is provided on each chip which has a subject latch point, the clock offset to which is to be measured. Test data distribution means is provided for distributing a test data signal from a test data source point to the data input of the reference latch point and to the data input of the associated latch point. Cross-transmission means are also provided for connecting together the data input of the reference latch point and the data input of the associated latch point. A pulse burst generator is connected to the clock source point in the system and a test data signal generator is connected to the test data signal source point. The test data signal generator responds to each burst of clock pulses by generating a logic level transition on the test data source point at a presettable time following a known one of the edges of the clock pulses in each burst. By adjusting the presettable delay in the test data signal generator, and observing the output of a given latch point after the last clock pulse in each burst reaches the clock input of the given latch point, a delay setting is determined at which the path delay for the following two paths are approximately equivalent: (1) the path from the clock source point through the clock distribution means to the clock input of the given latch point; and (2) the path from the clock source point through the test data signal generator, through the test data distribution means and to the data input of the given latch point.

US Patent:

50032569, Mar 26, 1991

Filed:

Sep 7, 1989

Appl. No.:

7/404312

Inventors:

John F. Merrill - Saratoga CA

Assignee:

Amdahl Corporation - Sunnyvale CA

International Classification:

G01R 3128

US Classification:

324158R

Abstract:

Method and apparatus are disclosed for measuring the clock offset between a reference latch point and a subject latch point in a system. In the system, an associated latch point is provided on each chip which has a subject latch point, the clock offset to which is to be measured. Test data distribution means is provided for distributing a test data signal from a test data source point to the data input of the reference latch point and to the data input of the associated latch point. Cross-transmission means are also provided for connecting together the data input of the reference latch point and the data input of the associated latch point. A pulse burst generator is connected to the clock source point in the system and a test data signal generator is connected to the test data signal source point. The test data signal generator responds to each burst of clock pulses by generating a logic level transition on the test data source point at a presettable time following a known one of the edges of the clock pulses in each burst. By adjusting the presettable delay in the test data signal generator, and observing the output of a given latch point after the last clock pulse in each burst reaches the clock input of the given latch point, a delay setting is determined at which the path delay for the following two paths are approximately equivalent: (1) the path from the clock source point through the clock distribution means to the clock input of the given latch point; and (2) the path from the clock source point through the test data signal generator, through the test data distribution means and to the data input of the given latch point.