Integrated Device Technologies, Inc. - Santa Clara CA
International Classification:
G11C 800
US Classification:
365233, 365191, 36518907
Abstract:
A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no âbus turnaroundâ down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.
Content Addressable Memory With Longest Match Detect
Thomas Diede - Cupertino CA John R. Mick - San Jose CA
Assignee:
Integrated Device Technology, Inc. - Santa Clara CA
International Classification:
G06F 1204
US Classification:
711108, 711103, 711100
Abstract:
A CAM system is provided for determining which data word in a CAM array exhibits the longest continuous, unmasked match with an input data value. The input data value is divided into non-overlapping subfields, thereby creating a series of keys, the first key of the series including either the least significant bit (LSB) or most significant bit (MSB) of the input data value. The CAM array is divided along columns into a similar series of non-overlapping sub-arrays corresponding to the subfields defined by the series of keys. A first CAM sub-array compares the first key with its stored rows of data bit values to generate a first match signal. The first match signal disables each row of the second CAM sub-array for which the corresponding row of the first CAM sub-array did not show a match. A second CAM sub-array then compares the second key with its enabled rows to generate a second match signal. The second match signal disables each row of the third CAM sub-array for which the corresponding row of either the first or second CAM sub-array did not show a match.
Pipelining A Content Addressable Memory Cell Array For Low-Power Operation
Chuen-Der Lien - Los Altos Hills CA John R. Mick - San Jose CA
Assignee:
Integrated Device Technology, Inc. - Santa Clara CA
International Classification:
G06F 1200
US Classification:
711108, 711168, 365 49
Abstract:
A content addressable memory (CAM) system that includes first and second CAM arrays, which generate first and second sets of match control signals, respectively, having higher and lower priorities, respectively. The first CAM array is enabled during a first memory cycle, and the first set of match control signals are analyzed. If a match exists in the first CAM array, a first priority encoder is enabled to process the first set of match control signals. If no match exists, the first priority encoder is not enabled, and a second memory cycle is initiated. The second CAM array is enabled during the second memory cycle, and the second set of signals is analyzed. If a match exists in the second CAM array, a second priority encoder is enabled to process the second set of match control signals. If no match exists, the second priority encoder is not enabled.
Integrated Device Technology, Inc. - Santa Clara CA
International Classification:
G11C 800
US Classification:
365233, 365191, 36518907
Abstract:
A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no âbus turnaroundâ down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.
Separate Byte Control On Fully Synchronous Pipelined Sram
A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. The logic circuit also detects which bytes of data are not to be written into the SRAM so that, during a read operation, those bytes not to be written into the SRAM are read from the SRAM in order to output a complete word corresponding to the value at the read address. No âbus turnaroundâ down time is experienced by the system thereby increasing the bandwidth of the system.
Integrated Device Technology, Inc. - Santa Clara CA
International Classification:
G11C 800
US Classification:
365233, 365191
Abstract:
A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no âbus turnaroundâ down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.
Content Addressable Memory (Cam) Devices That Perform Pipelined Multi-Cycle Look-Up Operations Using Cam Sub-Arrays And Longest Match Detection
Thomas Diede - Cupertino CA, US John R. Mick - Plano TX, US
Assignee:
NetLogic Microsystems, Inc. - Mountain View CA
International Classification:
G06F 12/04
US Classification:
711108, 711100, 711103
Abstract:
A CAM system is provided for determining which data word in a CAM array exhibits the longest continuous, unmasked match with an input data value. The input data value is divided into non-overlapping subfields, thereby creating a series of keys, the first key of the series including either the least significant bit (LSB) or most significant bit (MSB) of the input data value. The CAM array is divided along columns into a similar series of non-overlapping sub-arrays corresponding to the subfields defined by the series of keys. A first CAM sub-array compares the first key with its stored rows of data bit values to generate a first match signal. The first match signal disables each row of the second CAM sub-array for which the corresponding row of the first CAM sub-array did not show a match. A second CAM sub-array then compares the second key with its enabled rows to generate a second match signal. The second match signal disables each row of the third CAM sub-array for which the corresponding row of either the first or second CAM sub-array did not show a match.
Apparatus And Method For Matrix Memory Switching Element
John Mick - Alpine AZ, US Craig Lindahl - McKinney TX, US Yongdong Zhao - Pleasanton CA, US
Assignee:
Integrated Device Technology, Inc. - San Jose CA
International Classification:
H04L 12/56
US Classification:
370371, 370370, 370413, 370414, 370235
Abstract:
A matrixed memory array device is disclosed that includes input ports and output ports. Each input port is coupled to a first data bus and each output port is coupled to a second data bus that is different and separate from the first data bus. A memory brick is placed at each cross-point between first data buses and second data buses so as to switchably couple frames of data from input ports to output ports. Each memory brick contains a plurality of eight transistor (8-T) memory cells that can be used to store, erase, read, write, and switchably couple a data bit from the input port to a corresponding output port.
Name / Title
Company / Classification
Phones & Addresses
John Mick President
Werner - Mick Funeral Home Inc Werner Chapel For Funerals. Cremation Specialists Funeral Related Services. Cremation Services
3939 Lake Dr, previous address, Granite City, IL 62040 6189316317
John R. Mick General partner
JOHN R. MICK FAMILY LLLP
15 County Rd 2043, Alpine, AZ PO Box 46, Alpine, AZ 85920
John Mick Principal
2M Properties LLC Nonresidential Building Operator
5106 Yale Ct, Brentwood, TN 37027
John R. Mick President
MICK VENTURES, INC Business Services at Non-Commercial Site · Nonclassifiable Establishments
1009 Rubis Dr, Sunnyvale, CA 94087
Isbn (Books And Publications)
Data Broadcasting: Understanding the Atsc Data Broadcast Standard
Iptv Agile Methodologies Software Engineering Cloud Computing Software Development Vod Adaptive Streaming Product Management Integration Linux Ott Targeted Advertising Set Top Box Mpeg Streaming Media Mobile Devices System Architecture