John A Moran

US Patent:

7189610, Mar 13, 2007

Filed:

Oct 18, 2004

Appl. No.:

10/966519

Inventors:

John David Moran - Mesa AZ, US
Blanca Estela Kruse - Arizona City AZ, US
Jose Rogelio Moreno - Queen Creek AZ, US

Assignee:

Semiconductor Components Industries, L.L.C. - Phoenix AZ

International Classification:

H01L 21/8234

US Classification:

438237, 257E2704, 438328

Abstract:

In one embodiment, a diode is formed with anodes on two surfaces of a semiconductor substrate.

US Patent:

7820473, Oct 26, 2010

Filed:

Mar 21, 2005

Appl. No.:

11/084524

Inventors:

Linghui Chen - Gilbert AZ, US
Blanca Estela Kruse - Arizona City AZ, US
Mark Duskin - Scottsdale AZ, US
John D. Moran - Mesa AZ, US

Assignee:

Semiconductor Components Industries, LLC - Phoenix AZ

International Classification:

H01L 21/00

US Classification:

438 92, 438167, 438169, 438534, 438570, 257E21359, 257E21368

Abstract:

A Schottky diode capable of sustaining a voltage of greater than about 250 volts and a method for its manufacture. An epitaxial layer of N-type conductivity is disposed on a semiconductor substrate of N-type conductivity. A guard ring of P-type conductivity extends into the epitaxial layer from its surface. A stacked structure is formed on a portion of the guard ring and a portion of the epitaxial layer. The stacked structure includes a layer of semi-insulating semiconductor material disposed on a layer of dielectric material. A first metal layer is formed on the portion of the epitaxial layer adjacent a first side of the stacked structure and on a first portion of the stacked structure. A second metal layer is formed on the portion of the epitaxial layer adjacent a second side of the stacked structure and on a second portion of the stacked structure.

US Patent:

8501612, Aug 6, 2013

Filed:

Sep 20, 2007

Appl. No.:

11/858289

Inventors:

John D. Moran - Mesa AZ, US
Blanca Kruse - Maricopa AZ, US
Amilcar B. Gamez Sanchez - Chandler AZ, US

Assignee:

Semiconductor Components Industries, LLC - Phoenix AZ

International Classification:

H01L 21/44

US Classification:

438612, 257690

Abstract:

A flip chip structure includes glass stand-offs formed overlying a substrate surface. A conductive layer is formed overlying the glass stand-offs and configured for attaching to a next level of assembly. In one embodiment, photo glass processing is used to form the glass stand-offs.

US Patent:

57733686, Jun 30, 1998

Filed:

Jan 22, 1996

Appl. No.:

8/599457

Inventors:

John D. Moran - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2170

US Classification:

438742

Abstract:

A method of manufacturing a semiconductor component includes sputtering a first metal layer (16) over a substrate (11), sputtering a second metal layer (17) over the first metal layer (16), selectively etching the second metal layer (17) versus the first metal layer (16), selectively etching the first metal layer (16) versus the second metal layer (17), and thereafter, selectively re-etching the second metal layer (17) versus the first metal layer (16).

US Patent:

49771078, Dec 11, 1990

Filed:

Aug 23, 1989

Appl. No.:

7/397206

Inventors:

John D. Moran - Mesa AZ

Assignee:

Motorola Inc. - Schaumburg IL

International Classification:

H01L 21302

US Classification:

437225

Abstract:

Rectifiers of excellent characteristics may be more economically fabricated by a process in which a cavity is first etched in a non-epitaxial semiconductor wafer to a depth in the range of typically 15-25 percent of the initial wafer thickness. Simultaneous diffusion of N and P type dopants is used to provide (for an N type substrate) a P+ region in the bottom of the cavity and surrounding surface, and an N+ region on the opposite face of the wafer. A mask is then provided in the cavity bottom and the surrounding wafer regions etched to remove the P+ dopant outside the cavity thereby re-exposing the surrounding region of the original N type substrate. The P+ region may be level with or protrude slightly from the substrate surface. The junction formed between the P+ region in the cavity bottom and the N type substrate has a gradual contour where it intersects the surface thereby providing a more favorable field distribution. Passivation and metallization are provided in the conventional manner.

US Patent:

58048693, Sep 8, 1998

Filed:

Mar 31, 1997

Appl. No.:

8/829073

Inventors:

Peyman Hadizad - Scottsdale AZ
Ali Salih - Tempe AZ
John Robert Bender - Mesa AZ
John David Moran - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2358

US Classification:

257632

Abstract:

A semiconductor structure (10) uses a clamp (16) disposed at an edge (27) of a dielectric structure (14) in a semiconductor device. The clamp substantially reduces the separation or peeling of the dielectric structure or layer away from the underlying semiconductor material (20,24). The clamp also provides the benefit of protecting the interface between the dielectric layer and the underlying semiconductor material from chemical or moisture attack, either during later processing or after final manufacture. Such chemical or moisture attack and internal film stress are factors leading to separation of the dielectric film from the underlying semiconductor material. The clamp is useful, for example, in preventing separation of silicon nitride or oxide passivation from gallium arsenide substrates in power rectifier diodes.

US Patent:

50752596, Dec 24, 1991

Filed:

Aug 22, 1989

Appl. No.:

7/396713

Inventors:

John D. Moran - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 21208
H01L 21205

US Classification:

437230

Abstract:

Semiconductor device structures having very smooth surfaces and very high doping levels of opposite types present on the same wafer may be plated in the same electroless plating bath without differentiation between the N and P regions or rough and smooth surface regions. This is achieved by a pre-treatment involving coating the wafer surface with a metal salt (e. g. , NiCl in glycol and water) and reducing the metal salt in an oxygen free atmosphere (e. g. , hydrogen) at a temperature (e. g. , >300. degree. C. for Si) sufficient to promote formation of an intermetallic between the reduced metal and the semiconductor substrate. This provides very uniform and effective nucleation sites for the subsequent electroless plating process irrespective of the smoothness, doping type and doping density of the semiconductor surface.