John E O'Connor

US Patent:

6271726, Aug 7, 2001

Filed:

Jan 10, 2000

Appl. No.:

9/480831

Inventors:

Bert L. Fransis - San Diego CA
John Francis O'Connor - San Diego CA

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

H03F 345

US Classification:

330254

Abstract:

An amplifier circuit including a novel degeneration input stage that permits a low Noise Figure and superior linearity to be achieved in combination. The amplifier is suitable for use in fully integrated direct-conversion tuner circuits, and provides continuously variable gain functionality implemented by steering current away from an output load of the amplifier through differential transistor pairs located in the current signal paths of an input stage. Voltage headroom problems are avoided by placing the attenuation resistors of the degenerated input stage in the signal path, such that there is little or no DC voltage drop across the resistors. Further, this arrangement permits very accurate on-chip matching to an off-chip signal source. The distribution of IP3 values over the gain range of the amplifier, as well as gain and NF characteristics, are dependent on resistor ratios rather than absolute values. These amplifier characteristics are thus largely temperature and process independent.

US Patent:

55265278, Jun 11, 1996

Filed:

Oct 1, 1993

Appl. No.:

8/131210

Inventors:

Joseph T. Lipowski - Boxborough MA
Bjorn E. Bjerede - La Jolla CA
John F. O'Connor - San Diego CA

Assignee:

Pacific Communication Sciences, Inc. - San Diego CA

International Classification:

H04Q 732
H03L 700

US Classification:

4551831

Abstract:

Methods and apparatus for frequency synthesization are shown for generating an output signal of desired frequency. The frequency synthesizer includes an oscillator for generating an output signal at the desired frequency in response to a control signal. A first detector compares the output signal to a reference signal and generates a first difference signal representative of the differences, preferably in phase and frequency, between the output and the reference signals. A second detector compares the output signal to the reference signal and generates a second difference signal. A controller generates the control signal in response to either the first or second difference signal. A selector member selects between the first and second detectors to provide either the first or second control signal to the controller in response to a selection signal. A lock detector detects when the output signal and said reference signal are in a predetermined relation and generates the switch signal in response to the detection of the occurrence of such predetermined relation.