John R O'Donnell

US Patent:

46623728, May 5, 1987

Filed:

Aug 12, 1985

Appl. No.:

6/764404

Inventors:

Edward J. Sharkany - Huntington CT
John C. O'Donnell - Stratford CT

Assignee:

Acme United Corporation - Fairfield CT

International Classification:

A61B 1728

US Classification:

128321

Abstract:

By providing two cooperating, pivotable clamping arms, each of which incorporates an elongated, movement controlling plastic portion securely affixed to a die-cast metal or powdered metal section having a clamping face formed therein, a uniquely constructed, pivotable, jaw-clamping surgical instrument is attained. By employing die-cast metal or powdered metal sections, close tolerances and high quality is attained, while the expense of manufacture is substantially reduced. In addition, the integration of the die-cast metal or powdered metal sections with the elongated, movement controlling plastic arms achieves a trouble-free, dependable, inexpensive, disposable surgical instrument wherein the inherent advantages of both materials are optimized.

US Patent:

51796805, Jan 12, 1993

Filed:

May 30, 1991

Appl. No.:

7/707917

Inventors:

Robert P. Colwell - Guilford CT
John O'Donnell - Guilford CT
David B. Papworth - Guilford CT
Paul K. Rodman - Madison CT

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1208

US Classification:

395425

Abstract:

A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the instruction word. Each instruction field is associated with a bit of the mask word and accordingly, using the mask word, only non-zero instruction fields need to be stored in memory. The instruction compaction method is advantageously used in a high speed cache miss engine for refilling portions of instruction cache after a cache miss occurs.

US Patent:

D2958937, May 24, 1988

Filed:

Sep 25, 1985

Appl. No.:

6/780009

Inventors:

Edward J. Sharkany - Huntington CT
John C. O'Donnell - Stratford CT

Assignee:

Acme United Corporation - Fairfield CT

US Classification:

D24 27

US Patent:

48335991, May 23, 1989

Filed:

Apr 20, 1987

Appl. No.:

7/041081

Inventors:

Robert P. Colwell - Guilford CT
John O'Donnell - Guilford CT
David B. Papworth - Guilford CT
Paul K. Rodman - Madison CT

Assignee:

Multiflow Computer, Inc. - Branford CT

International Classification:

G06F 928
G06F 942

US Classification:

364200

Abstract:

In a parallel data processing system having a plurality of separately operating arithmetic processing units, a method and apparatus allows a plurality of branch instructions to be operated upon in a single machine cycle. The branch instructions have associated therewith a hierarchical priority system and the method and apparatus determine which branch, if any, should be taken. In particular, the method and apparatus simultaneously determine, during the parallel execution of the branch instructions, whether any branch test condition associated with a branch instruction is true, and independently, the target address for each branch instruction and a fall-through instruction address if a branch instruction is not taken.

US Patent:

49204777, Apr 24, 1990

Filed:

Apr 20, 1987

Appl. No.:

7/040990

Inventors:

Robert P. Colwell - Guilford CT
John O'Donnell - Guilford CT
David B. Papworth - Guilford CT
Paul K. Rodman - Madison CT

Assignee:

Multiflow Computer, Inc. - Branford CT

International Classification:

G06F 1208
G06F 938
G06F 1100

US Classification:

364200

Abstract:

A data processor has a central processing unit and at least one pipelined memory controller circuitry. The central processing unit addresses data in the memory using a virtual address memory table lookaside buffer and features a data miss recovery circuitry wherein, after a memory access error condition has been detected, the instruction causing the error condition, and those instructions entering the memory pipeline after the instruction causing the error condition, are replayed. The method and apparatus for replaying the instructions use first in-first out buffers for storing the virtual address data and instruction status data relating to each memory access instruction. That stored data is then retrieved after an error condition is detected so that the instruction sequence, beginning at the data miss, can be replayed.

US Patent:

D2958945, May 24, 1988

Filed:

Sep 26, 1985

Appl. No.:

6/780215

Inventors:

Edward J. Sharkany - Huntington CT
John C. O'Donnell - Stratford CT

Assignee:

Acme United Corporation - Fairfield CT

US Classification:

D24 28

US Patent:

50578375, Oct 15, 1991

Filed:

Jan 30, 1990

Appl. No.:

7/476108

Inventors:

Robert P. Colwell - Guilford CT
John O'Donnell - Guilford CT
David B. Papworth - Guilford CT
Paul K. Rodman - Madison CT

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

H03M 500

US Classification:

341 55

Abstract:

A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the instruction word. Each instruction field is associated with a bit of the mask word and accordingly, using the mask word, only non-zero instruction fields need to be stored in memory. The instruction compaction method is advantageously used in a high speed cache miss engine for refilling portions of instruction cache after a cache miss occurs.

US Patent:

53075064, Apr 26, 1994

Filed:

Sep 16, 1992

Appl. No.:

7/945571

Inventors:

Robert P. Colwell - Guilford CT
John O'Donnell - Guilford CT
David B. Papworth - Guilford CT
Paul K. Rodman - Madison CT

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1340

US Classification:

395800

Abstract:

A parallel processor has a plurality of communication buses advantageously interconnecting the arithmetic processor elements, the memory controller elements, a global controller circuitry, and input/output processors. The processor preferably has at least one central processing unit cluster, the cluster having at least one integer processor and one floating point processor. A plurality of I/F buses interconnect the integer and floating point processors of a cluster for communications therebetween. Integer load buses connect the integer processors of each cluster and selectively connect those processors to the memory controllers for transferring data from memory to the clusters and for providing inter-integer processor data communications. A plurality of floating point load buses connect the floating point processors of the clusters to selected memory controllers for transferring data from the controllers to the floating point processors and for providing inter-floating point processor data communications. A plurality of physical address buses provide one-way communications for transferring memory addresses from the integer processors to the memories and a plurality of storage buses connect the floating point processors to the memory controllers along a one-way communications path for transferring data to be stored in the memories.