John H O'Leary

US Patent:

20060254898, Nov 16, 2006

Filed:

May 10, 2006

Appl. No.:

11/382539

Inventors:

John O'Leary - Edmonds WA, US

International Classification:

H01H 3/40

US Classification:

200500000

Abstract:

A haptic data input device is shown and described.

US Patent:

20190364036, Nov 28, 2019

Filed:

May 22, 2019

Appl. No.:

16/419186

Inventors:

- Mountain View CA, US
Ari Chivukula - Seattle WA, US
Norman Scott Storkel - Mountain View CA, US
Steven Shenker - Cape Town, ZA
Eric Shrewsberry - Palo Alto CA, US
Phang Moh Lim - Setia Alam, MY
John O'Leary - Golden CO, US

Assignee:

Simtek, Inc. - Mountain View CA

International Classification:

H04L 29/06
H04L 29/08
H04W 4/60
H04W 12/00
G06K 7/14

Abstract:

The present disclosure generally relates systems, apparatus, and methods for security devices, in particular, low-power, security devices and other devices. The devices typically connect to the Internet or other networks only on an intermittent, event-based basis, typically by cellular modem. The invention meets a need for security devices, as well as other devices, that can connect to the Internet and other networks but that are low-power and/or intermittently connected to networks such as the Internet on an intermittent and/or on demand basis. This renders them more secure, less susceptible to hacking and other attacks, less prone to continuously gathering data that a user might consider to be superfluous and/or invasive in terms of data collected, and can make them low-power, thus allowing them to run on battery for long periods of time.

US Patent:

20180309461, Oct 25, 2018

Filed:

Mar 15, 2018

Appl. No.:

15/922642

Inventors:

- Santa Clara CA, US
David M. Russinoff - Austin TX, US
Amit Gradstein - Binyamina, IL
John W. O'Leary - Portland OR, US
Zeev Sperber - Zichron Yackov, IL

International Classification:

H03M 7/30
G06F 9/30
G06F 15/80

Abstract:

An apparatus and method are described for performing vector compression. For example, one embodiment of a processor comprises: vector compression logic to compress a source vector comprising a plurality of valid data elements and invalid data elements to generate a destination vector in which valid data elements are stored contiguously on one side of the destination vector, the vector compression logic to utilize a bit mask associated with the source vector and comprising a plurality of bits, each bit corresponding to one of the plurality of data elements of the source vector and indicating whether the data element comprises a valid data element or an invalid data element, the vector compression logic to utilize indices of the bit mask and associated bit values of the bit mask to generate a control vector; and shuffle logic to shuffle/permute the data elements of the source vector to the destination vector in accordance with the control vector.

US Patent:

20160094241, Mar 31, 2016

Filed:

Sep 26, 2014

Appl. No.:

14/499038

Inventors:

- SANTA CLARA CA, US
David M. Russinoff - Austin TX, US
Amit Gradstein - Binyamina, IL
John W. O'Leary - Portland OR, US
Zeev Sperber - Zichron Yackov, IL

International Classification:

H03M 7/30
G06F 17/16

Abstract:

An apparatus and method are described for performing vector compression. For example, one embodiment of a processor comprises: vector compression logic to compress a source vector comprising a plurality of valid data elements and invalid data elements to generate a destination vector in which valid data elements are stored contiguously on one side of the destination vector, the vector compression logic to utilize a bit mask associated with the source vector and comprising a plurality of bits, each bit corresponding to one of the plurality of data elements of the source vector and indicating whether the data element comprises a valid data element or an invalid data element, the vector compression logic to utilize indices of the bit mask and associated bit values of the bit mask to generate a control vector; and shuffle logic to shuffle/permute the data elements of the source vector to the destination vector in accordance with the control vector.