John W Owens

US Patent:

7100026, Aug 29, 2006

Filed:

May 30, 2001

Appl. No.:

09/871301

Inventors:

William J. Dally - Stanford CA, US
Scott Rixner - Spring TX, US
John D. Owens - Emeryville CA, US
Ujval J. Kapasi - Santa Clara CA, US

Assignee:

The Massachusetts Institute of Technology - Cambridge MA
The Board of Trustees of the Leland Stanford Junior University - Palo Alto CA

International Classification:

G06F 7/38

US Classification:

712222, 712 4, 712 8, 712 22, 718105

Abstract:

A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processed at full processor efficiency without cycles wasted due to branch latency. Data to be processed are divided into two groups based on whether or not they satisfy a given condition by, e. g. , steering each to one of two index vectors. Once the data have been segregated in this way, subsequent processing can be performed without conditional operations, processor cycles wasted due to branch latency, incorrect speculation or execution of unnecessary instructions due to predication. Other examples of conditional operations include combining one or more input vectors into a single output vector based on a condition vector, conditional vector switching, conditional vector combining, and conditional vector load balancing.

US Patent:

7589719, Sep 15, 2009

Filed:

Jul 15, 2005

Appl. No.:

11/182632

Inventors:

John Owens - Berkeley CA, US
Andy Riffel - Davis CA, US
Aaron Lefohn - Oakland CA, US
Kiril Vidimce - San Francisco CA, US
Mark Leone - Walnut Creek CA, US

Assignee:

The Regents of the University of California - Oakland CA
Pixar - Emeryville CA

International Classification:

G06T 15/00
G06T 1/00
G06F 9/46

US Classification:

345419, 345522, 718103, 718104

Abstract:

Computer operations are partitioned for execution by a processor. A plurality of operations to be partitioned is received. The respective priorities for each of the plurality of operations is determined. Ready operations are identified, where a ready operation is an operation that does not have any predecessor operations that have not yet been added to a partition. A determination is made whether adding the ready operations with the highest priorities to the current partition would violate a hardware resource constraint. Based on this determination, the ready operations are added to the partition. The operations added to the partition are provided to a processor for execution.

US Patent:

62694359, Jul 31, 2001

Filed:

Sep 14, 1998

Appl. No.:

9/152944

Inventors:

William J. Dally - Stanford CA
Scott Whitney Rixner - Mountain View CA
John Owens - Menlo Park CA
Ujval J. Kapasi - Standford CA

Assignee:

The Board of Trustees of the Leland Stanford Junior University - Stanford CA
The Massachusetts Institute of Technology - Cambridge MA

International Classification:

G06F 9305

US Classification:

712 8

Abstract:

A processor implements conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processed at full processor efficiency without cycles wasted due to branch latency. Data to be processed is divided into two groups based on whether or not they satisfy a given condition by, e. g. , steering each to one of two index vectors. Once the data has been segregated in this way, subsequent processing can be performed without conditional operations, processor cycles wasted due to branch latency, incorrect speculation or execution of unnecessary instructions due to predication.