John S Packer

US Patent:

6373794, Apr 16, 2002

Filed:

Jan 19, 2001

Appl. No.:

09/765837

Inventors:

John S. Packer - San Jose CA

Assignee:

STMicroelectronics N.V.

International Classification:

G11B 1722

US Classification:

369 3023, 369 5926, 714769

Abstract:

Disclosed is a disc drive system that includes a digital signal processor for processing information sectors read from a CD media. The digital signal processor is configured to parse the information sectors into data frames and subcode frames. A data auto-start unit for triggering a data transfer to a buffer memory when a desired data frame is detected. A subcode auto-start unit for triggering a subcode transfer to the buffer memory when a desired subcode frame is detected. Preferably, the desired data frame and the desired subcode frame have a same MSF. The disc drive system further includes a buffer manager having a plurality of counters that are configured to track the number of data frames and the number of subcode frames being transferred to the buffer memory, and releasing a block including one of the data frames and one of the subcode frames when the counters indicate that the block is complete.

US Patent:

6449111, Sep 10, 2002

Filed:

Sep 15, 1998

Appl. No.:

09/153788

Inventors:

Fred A. Kool - Aptos CA
John S. Packer - Milpitas CA

Assignee:

Adaptec, Inc. - Milpitas CA

International Classification:

G11B 509

US Classification:

360 48, 360 51, 360 7708, 360 53

Abstract:

Write and read processes for a disk drive handle data and overhead fields in a data frame that extends between two servo sectors on a disk. A write process fills a buffer with both data values and overhead values sufficient to fill a data frame and then writes the entire data frame based on the values in the buffer. Accordingly, activation of a separate formatting circuit is not required as those fields are written, and the write operation does not require sector pulses to control the timing for writing individual data sectors in the data frame. The overhead fields written include VFO fields and data synchronization fields. The read process uses timing signals derived from detection of servo sectors and data synchronization fields but otherwise sequentially reads data and overhead fields and transfers those fields to a buffer. The data in a requested sector can be separated from overhead information and data of other sectors in the buffer, when the disk drive outputs the requested data.

US Patent:

6751693, Jun 15, 2004

Filed:

Mar 2, 2001

Appl. No.:

09/798278

Inventors:

Charles A. Monia - San Jose CA
John S. Packer - San Jose CA

Assignee:

Adaptec, Inc. - Milpitas CA

International Classification:

G06F 1300

US Classification:

710104, 710 8, 713100

Abstract:

The present invention provides a method for assigning addresses to expanded devices in a computer I/O subsystem, which has one or more buses. Each bus has an N-bit data bus for communication. One or more types of expanded devices are provided in the computer I/O subsystem and are coupled to one or more peripheral buses. An expanded address space is defined for the one or more types of expanded devices by partitioning an N-bit data bus into a pair of fields that includes an expanded ID field and an expanded signature field. An address is assigned to each of the expanded devices by assigning an expanded signature to each type of the expanded devices. In addition, an expanded ID is assigned to each expanded device within each type of the expanded devices, wherein more than two bits are asserted in the address.

US Patent:

6754720, Jun 22, 2004

Filed:

Mar 2, 2001

Appl. No.:

09/798275

Inventors:

John S. Packer - San Jose CA

Assignee:

Adaptec, Inc. - Milpitas CA

International Classification:

G06F 300

US Classification:

710 3, 710 2, 710 4, 710 8, 710 9, 710 15, 710104, 711 1, 709234

Abstract:

The present invention provides methods for automatically assigning addresses to expanders in a computer I/O subsystem that is coupled to one or more host computers. The computer I/O subsystem includes one or more peripheral buses, a set of peripheral devices, and a set of expanders with each expander being arranged to couple a pair of peripheral buses. The peripheral devices are coupled to the peripheral buses. In this configuration, a host computer selects a peripheral device as a target device and writes an address data pattern to the selected target device. The host computer then selects the target device and reads the address data pattern from the target device. Unique addresses are then assigned to one or more expanders coupling the host computer and the target device starting from the address data pattern, preferably by incrementing the address data pattern.

US Patent:

6804739, Oct 12, 2004

Filed:

Feb 5, 2002

Appl. No.:

10/068651

Inventors:

B. Arlen Young - Palo Alto CA
John S. Packer - San Jose CA
Wei Chuan Goh - Singapore, SG

Assignee:

Adaptec, Inc. - Milpitas CA

International Classification:

G06F 1338

US Classification:

710300, 710 31, 370230, 709224

Abstract:

A SCSI selective options message delay expander includes a capability for monitoring messages transferred between a first port and a second port of the expander, for delaying a pre-selected message, for modifying the delayed pre-selected message, and for storing information obtained from the delayed pre-selected message. The ability to change messages allows the expander to be used with SCSI initiators and/or SCSI target devices that have SCSI characteristics different from the SCSI characteristics of the expander.

US Patent:

6816915, Nov 9, 2004

Filed:

Mar 2, 2001

Appl. No.:

09/798100

Inventors:

John S. Packer - San Jose CA

Assignee:

Adaptec, Inc. - Milpitas CA

International Classification:

G06F 300

US Classification:

710 2, 710 62, 710 74, 710300

Abstract:

The present invention provides methods for automatically discovering topology map of an I/O subsystem. The I/O subsystem is coupled to one or more host computers and includes one or more peripheral buses, a set of peripheral devices, and a set of expanders with each expander having a valid expander address and being arranged to couple a pair of the peripheral buses. The peripheral devices and the one or more host computers are coupled to the peripheral buses. A host computer selects a peripheral device as a target device and writes a set of entries to the selected target device. Each entry written an expander address field initialized to an invalid expander address for storing an expander address. The host computer then selects the target device and reads the set of entries from the target device. For each expander coupled between the host computer and the target device, the valid expander address associated with the each expander is assigned to one of the expander address fields in the set of entries that contain invalid expander addresses.

US Patent:

6862642, Mar 1, 2005

Filed:

May 15, 2001

Appl. No.:

09/858321

Inventors:

John S. Packer - San Jose CA, US
Lawrence J. Lamers - San Jose CA, US

Assignee:

Adaptec, Inc. - Milpitas CA

International Classification:

G06F013/00
G06F013/36
G06F012/16
H03K019/03

US Classification:

710300, 710312, 326 9, 711100

Abstract:

Expander device and method for resetting bus segments in I/O subsystem to clear bus hang in an I/O subsystem having a plurality of bus segments. Each bus segment in the I/O subsystem includes a set of devices and a bus that is coupled to the set of devices. In addition, the I/O subsystem includes at least one expander, each expander being arranged to couple a pair of buses for propagating communication signals. A reset signal is asserted on a first bus segment. In response to the reset signal, each expander coupled to the first bus segment and each device in the first bus segment reset themselves. Additionally, each expander coupled to the first bus segment isolates the reset signal such that the reset signal is not propagated to the other bus segments. For each expander coupled to the first bus segment, all communication signals are isolated such that each expander prevents propagation of the communication signals between the first bus and other bus. Then, it is determined whether the other bus is no longer hung for each expander coupled to the first bus segment.

US Patent:

6948024, Sep 20, 2005

Filed:

May 1, 2001

Appl. No.:

09/846975

Inventors:

John S. Packer - San Jose CA, US
Lawrence J. Lamers - San Jose CA, US

Assignee:

Adaptec, Inc. - Milpitas CA

International Classification:

G06F013/20

US Classification:

710313, 710306

Abstract:

An expander device and method for isolating bus segments from one another in an I/O subsystem. The expander device is arranged to couple the bus segments for communication in the I/O subsystem. The expander device includes a first I/O interface circuit, a second I/O interface circuit, and an expander controller. The first I/O interface circuit is configured to be coupled to a first bus segment and is adapted to interface input and output communication signals with the first bus segment. The second I/O interface circuit is configured to be coupled to a second bus segment and is adapted to interface the input and output communication signals with the second bus segment. The expander controller is coupled to communicate the input and output communication signals between the first and second I/O interface circuits. The expander controller is further arranged to control communication between the bus segments and includes a segment controller adapted to generate a first signal. The segment controller provides the first signal to the first and second I/O interface circuits to disable output of the communication signals from the first and second I/O interface circuits to the first and second bus segments.