John S Pieper

US Patent:

7363195, Apr 22, 2008

Filed:

Jul 1, 2005

Appl. No.:

11/174022

Inventors:

Jeffrey M. Parker - Cedar Park TX, US
Wayne G. Renken - San Jose CA, US
John B. Pieper - Coralville IA, US

Assignee:

Sensarray Corporation - Santa Clara CA

International Classification:

G06F 17/40
G06F 19/00

US Classification:

702183, 702188, 702187

Abstract:

A sensor network collects time-series data from a process tool and supplies the data to an analysis system where pattern analysis techniques are used to identify structures and to monitor subsequent data based on analysis instructions or a composite model. Time-series data from multiple process runs are used to form a composite model of a data structure including variation. Comparison with the composite model gives an indication of tool health. A sensor network may have distributed memory for network configuration.

US Patent:

8046193, Oct 25, 2011

Filed:

Apr 21, 2008

Appl. No.:

12/107007

Inventors:

Jeffrey M. Parker - Cedar Park TX, US
Wayne G. Renken - San Jose CA, US
John B. Pieper - Coralville IA, US

Assignee:

KLA-Tencor Corporation - Milpitas CA

International Classification:

G06F 17/40
G06F 19/00

US Classification:

702183, 702182, 702 84

Abstract:

A sensor network collects time-series data from a process tool and supplies the data to an analysis system where pattern analysis techniques are used to identify structures and to monitor subsequent data based on analysis instructions or a composite model. Time-series data from multiple process runs are used to form a composite model of a data structure including variation. Comparison with the composite model gives an indication of tool health. A sensor network may have distributed memory for a more simplified configuration.

US Patent:

20030005419, Jan 2, 2003

Filed:

Oct 12, 1999

Appl. No.:

09/416436

Inventors:

JOHN SAMUEL PIEPER - MONT VERNON NH, US
STEVEN ORODON HOBBS - WESTFORD MA, US
STEPHEN CORRIDON ROOT - WESTBORO MA, US

International Classification:

G06F009/45

US Classification:

717/141000

Abstract:

A technique is provided for inserting memory prefetch instructions only at appropriate locations in program code. The instructions are inserted into the program code such that, when the code is executed, the speed and efficiency of execution of the code may be improved, cache conflicts arising from execution of the prefetch instruction may be substantially eliminated, and the number of simultaneously-executing memory prefetch operations may be limited to prevent stalling and/or overtaxing of the processor executing the code.