John Matthew Robbins

US Patent:

8268696, Sep 18, 2012

Filed:

Dec 9, 2010

Appl. No.:

12/964430

Inventors:

Scott R. Summerfelt - Garland TX, US
Stephen A. Meisner - Allen TX, US
John B. Robbins - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/762

US Classification:

438401, 438462, 438975, 257797, 257E21525, 257E23001, 257E23179

Abstract:

An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.

US Patent:

8324742, Dec 4, 2012

Filed:

Aug 1, 2008

Appl. No.:

12/185003

Inventors:

Scott R. Summerfelt - Garland TX, US
Stephen A. Meisner - Allen TX, US
John B. Robbins - McKinney TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 23/544
H01L 21/76

US Classification:

257797, 257E21521, 257 23179, 438401, 438462, 438975

Abstract:

An IC alignment mark in a contact metal layer for use under an opaque layer, and a process for forming the alignment mark, are disclosed. The alignment mark includes contact metal fields, each several microns wide, with an array of PMD pillars in the interior, formed during contact etch, contact metal deposition and selective contact metal removal processes. The pillars are arrayed such that all exposed surfaces of the contact metal are planar. One configuration is a rectangular array in which every other row is laterally offset by one-half of the column spacing. Horizontal dimensions of the pillars are selected to maximize the contact metal fill factor, while providing sufficient adhesion to the underlying substrate during processing. The contact metal is at least 15 nanometers lower than the PMD layer surrounding the alignment mark, as a result of the contact metal removal process.

US Patent:

51972719, Mar 30, 1993

Filed:

Mar 22, 1981

Appl. No.:

7/674822

Inventors:

John Robbins - Sherman TX
Ricky L. Boston - Denison TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

B24B 104

US Classification:

511631

Abstract:

A method of backside damaging a silicon semiconductor wafer by abrading the wafer in an abrasive powder is disclosed. The wafer is rotated or translated in the powder while the powder is being vibrated. A fixture holds one or more semiconductor wafers during the processing and allows the wafer to be rotated during processing if desired.

US Patent:

50064754, Apr 9, 1991

Filed:

Jul 12, 1989

Appl. No.:

7/378632

Inventors:

John Robbins - Sherman TX
Ricky L. Boston - Denison TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21306

US Classification:

437 10

Abstract:

A method of backside damaging a silicon semiconductor wafer by abrading the wafer in an abrasive powder is disclosed. The wafer is rotated or translated in the powder while the powder is being vibrated. A fixture holds one or more semiconductor wafers during the processing and allows the wafer to be rotated during processing if desired.

US Patent:

49350641, Jun 19, 1990

Filed:

Mar 28, 1988

Appl. No.:

7/173837

Inventors:

John B. Robbins - Sherman TX
Lawrence D. Dyer - Richardson TX
Mohendra S. Bawa - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

C03C 2300

US Classification:

134 2

Abstract:

Trace quantities of elemental iodine are added to deionized water used in the manufacture of semiconductor materials and devices in order to sterilize the water and the delivery system of microscopic life forms, and to leave the iodine in the flow all the way through processing except for those process steps where iodine may be detrimental to the process step.

US Patent:

54242240, Jun 13, 1995

Filed:

Jan 19, 1993

Appl. No.:

8/005713

Inventors:

Franklin L. Allen - Sherman TX
Eugene C. Davis - Sherman TX
Lawrence D. Dyer - Richardson TX
Jerry B. Medders - Van Alstyne TX
Vikki S. Simpson - Sherman TX
Jerry D. Smith - Sherman TX
Michael Cunningham - Anna TX
John B. Robbins - Sherman TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21306

US Classification:

437 10

Abstract:

The protection to the backside of the semiconductor wafer is accomplished by applying a layer of silicon oxide or silicon nitride or other deposited material to the back surface of a semiconductor wafer to protect against particles, scratches, and etching by mild caustic solutions. The layer remains in place during all three processes, edge pre-polish, mirror edge polish, and wafer polish.

US Patent:

20150187570, Jul 2, 2015

Filed:

Aug 25, 2014

Appl. No.:

14/467688

Inventors:

- Dallas TX, US
John Britton ROBBINS - McKinney TX, US

International Classification:

H01L 21/02

Abstract:

Use of a non-solvent for the edge bead removal of spin-coated PZT or PLZT thinfilms, eliminates swelling of the exposed edges of the PZT or PLZT thinfilms and eliminates delamination and formation of particle defects in subsequent bake and anneal steps.

US Patent:

20140111301, Apr 24, 2014

Filed:

Oct 18, 2012

Appl. No.:

13/655419

Inventors:

- Dallas TX, US
John Britton Robbins - McKinney TX, US

Assignee:

TEXAS INSTRUMENTS INCORPORATED - Dallas TX

International Classification:

H01C 1/012
H01L 21/02

US Classification:

338308, 438382, 257E21004

Abstract:

The resistance of a thin-film resistor is substantially increased by forming the thin-film resistor to line one or more non-conductive trenches. By lining the one or more non-conductive trenches, the overall length of the resistor is increased while still consuming approximately the same surface area as a conventional resistor.