John E Rudy

US Patent:

20130282807, Oct 24, 2013

Filed:

Apr 20, 2012

Appl. No.:

13/452234

Inventors:

John Edward Rudy - Escondido CA, US
An Tonthat - San Diego CA, US
Patrick Charles Murray - San Diego CA, US

Assignee:

Combined Conditional Access Development and Support, LLC - San Diego CA

International Classification:

G06F 15/16

US Classification:

709204

Abstract:

Aspects of the disclosure relate to a protocol for communication of information. The protocol can be a non-standard universal serial bus (USB) protocol and can guarantee bandwidth and latency for information communication between a USB host and a single USB device. In one aspect, the non-standard USB protocol can employ a repeating message sequence that is fixed, or static, and preconfigured, the sequence comprising alternating transmission of messages between a first device (e.g., a host device) and a second device (e.g., a peripheral device).

US Patent:

43440754, Aug 10, 1982

Filed:

Aug 28, 1980

Appl. No.:

6/181984

Inventors:

John E. Rudy - Lancaster PA

Assignee:

RCA Corporation - New York NY

International Classification:

G09G 128

US Classification:

340703

Abstract:

Ragged vertical edges normally displayed by a NTSC color-carrier on a non-interlaced display are effectively eliminated through persistence of vision by altering the duration of a selected single scan-line of the non-display portion of each of successive fields by an odd number of half-cycles of the NTSC color-carrier frequency.

US Patent:

48127426, Mar 14, 1989

Filed:

Dec 3, 1987

Appl. No.:

7/127972

Inventors:

Kenneth N. Abel - Vista CA
John E. Rudy - Poway CA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G01R 3102

US Classification:

324 73R

Abstract:

This invention is an improvement to an integrated circuit package which is of a type that includes a package body with multiple chip attach regions for holding respective integrated circuit chips, signal pads around the chip attach regions, an array of I/O pins on the package body, a first set of conductors in the package body which selectively connect some of the signal pads to the I/O pins, and a second set of conductors which selectively connect some of the signal pads to each other but not to any I/O pins. This improvement enhances the testability of the package at its intermediate state of manufacture, and it comprises: (a) a test region in the package body which is spaced apart from the I/O pins, the chip attach regions, the signal pads, and the first and second sets of conductors; (b) an array of test pins which is attached to the test region of the package body; and (c) a third set of conductors which are disposed in the package body that selectively connect the I/O pins to the signal pads and the first and second sets of conductors such that all conductive paths can be tested for shorts and/or opens via the test pins and the I/O pins. Then, after testing is complete, the test region of the package body is permanently removed from the remainder of the package by a step such as sawing.

US Patent:

54715890, Nov 28, 1995

Filed:

Sep 8, 1993

Appl. No.:

8/118164

Inventors:

Isam W. Akkawi - Aptos CA
Scott H. Hayashida - San Diego CA
Vivek Ladha - Santa Clara CA
John E. Rudy - Poway CA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 1300

US Classification:

395800

Abstract:

A multiprocessor data processing system comprises a plurality of unsymmetrically connected data processing nodes; where the total number of nodes is more than 2. sup. n-1 and less than 2. sup. n, and n is an integer larger than two Each node has n input/output channels which respectively are channel(0), channel(1), channel(2), etc. ; each node has a binary address b. sub. n-1. . . b. sub. 1 b. sub. 0 which runs consecutively from node to node; each pair of nodes whose binary addresses differ by only one binary bit b. sub. x are interconnected by a channel(x) to channel(x) connection; and, at least one pair of nodes whose binary addresses differ by two binary bits b. sub. x and b. sub. y are interconnected by a channel(x) to channel(y) connection, where x and y=0,1,. . . n-1. To establish a route from any one node to any other node, channels are selected which decrease the distance to the destination by two nodes or one node or maintain the same distance.