John L Schell

US Patent:

6748488, Jun 8, 2004

Filed:

Sep 28, 2001

Appl. No.:

09/966842

Inventors:

James Byrd - Milpitas CA
Ebrahim Hashemi - Los Gatos CA
Manuel Cisneros - San Carlos CA
Alex Umino - Cupertino CA
John Schell - Westminster CO

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711114, 714770

Abstract:

A data storage subsystem including an array of storage devices and a storage controller is disclosed. In one embodiment, the array of storage devices stores information in multiple stripes. Each stripe may include a plurality of data blocks and redundancy information in the form of plurality of redundancy blocks. The redundancy information may be generated using an nth order generator polynomial such as a Reed Solomon code. The storage controller may be configured to perform modified read/write stripe updates by: (a) reading original data from a subset of data blocks in a target stripe; (b) reading the original redundancy information for that stripe; (c) comparing the original data with the new data to determine a data difference; (d) calculating a redundancy difference from the data difference; (e) applying the redundancy difference to the original redundancy information to obtain updated redundancy information, (f) writing the new data and updated redundancy information to the target stripe. Multiple erasure correction is also contemplated.

US Patent:

57649316, Jun 9, 1998

Filed:

May 31, 1996

Appl. No.:

8/656641

Inventors:

Kenneth A. Schmahl - San Jose CA
Matthew J. Tedone - Sunnyvale CA
John C. Schell - Sunnyvale CA
Igor Karminsky - San Jose CA
Ray P. Chan - Cupertino CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

G06F 1314
G06F 1338

US Classification:

395287

Abstract:

A method for passing mastership of a bus is described. According to the method, it is determined whether to use the bus. If the bus is to be used, it is determined whether the bus is available. If the bus is available, the bus is accessed and a signal is generated to indicate that the bus is being accessed. A timer is also started and access to the bus is yielded when the timer expires. A processor that passes mastership to a shared resource is also described. The processor comprises a resource accessing unit. The resource accessing unit allows the processor to access a resource upon receiving a first signal from a component coupled to the resource. The resource accessing unit yields access of the resource to the component upon receiving a second signal from the component.

US Patent:

59700700, Oct 19, 1999

Filed:

Aug 20, 1997

Appl. No.:

8/915286

Inventors:

Kin M. Ho - Fremont CA
David C. Banks - Pleasanton CA
John C. Schell - Sunnyvale CA
Tai Quan - San Jose CA
Teshager Tesfaye - Mountain View CA
Kenneth A. Schmahl - San Jose CA
Matthew J. Tedone - Sunnyvale CA
Drew G. Doblar - San Jose CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H04J 302

US Classification:

370462

Abstract:

A method, in a host adapter circuit configured for coupling a host electronic device with one of a fiber channel loop and a point-to-point communication channel, for receiving data at the host adapter circuit from one of the fiber channel loop and the point-to-point communication channel. The method includes providing a selectable control signal configured for indicating whether the host adapter circuit is coupled to the fiber channel loop or the point-to-point communication channel. The method further includes providing a front-end receive circuit. The front-end receive circuit is configured for coupling with an input data port. The input data port represents one of the fiber channel loop and the point-to-point communication channel. The method also includes coupling the front-end receive circuit with the selectable control signal. Additionally, the method includes coupling an output of the front-end receive circuit with a decoder of the host adapter circuit, wherein the front-end receive circuit is configured to process, responsive to the selectable control signal, either fiber channel loop data from the fiber channel loop or point-to-point data from the point-to-point communication channel from the input data port to provide parallel data having a predefined size to the decoder circuit.

US Patent:

6038235, Mar 14, 2000

Filed:

Aug 20, 1997

Appl. No.:

8/915135

Inventors:

Kin M. Ho - Fremont CA
David C. Banks - Pleasanton CA
John C. Schell - Sunnyvale CA
Tai Quan - San Jose CA
Teshager Tesfaye - Mountain View CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H04J 302

US Classification:

370462

Abstract:

A method for automatically arbitrating for mastership of a fiber channel loop in a host adapter circuit configured for coupling a host electronic device with the fiber channel loop. The host adapter circuit has a processor and a loop control circuit different from the processor. The loop control circuit is coupled to a memory of the host adapter circuit. The method includes sending out a host ARBITRATE primitive on the fiber channel loop. The method further includes employing the loop control circuit to monitor received ARBITRATE primitives received at the host adapter circuit from the fiber channel loop. There is also included ascertaining, using the loop control circuit, whether one of the received ARBITRATE primitives represents the host ARBITRATE primitive sent out previously. If the one of the received ARBITRATE primitives represents the host ARBITRATE primitive sent out previously, the method includes placing a target device coupled to the fiber channel loop in an OPENED state for receiving data from the host electronic device.