John S Spence

Address:

4916 Silent Vly Ave, Las Vegas, NV 89139

VIN:

1HD1FC4197Y666551

Make:

Cadillac

Model:

Escalade ESV AWD 4dr

Year:

2007

US Patent:

6415376, Jul 2, 2002

Filed:

Jun 16, 2000

Appl. No.:

09/595791

Inventors:

Moataz A Mohamed - Irvine CA
Chien-Wei Li - Mission Viejo CA
John R. Spence - Villa Park CA

Assignee:

Conexant Sytems, Inc. - Newport Beach CA

International Classification:

G06F 938

US Classification:

712 24, 712204, 712206, 712210, 712213, 712215

Abstract:

An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit.

US Patent:

6549986, Apr 15, 2003

Filed:

Jun 20, 2000

Appl. No.:

09/598063

Inventors:

John R. Spence - Villa Park CA

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

G06F 1202

US Classification:

711125

Abstract:

A low power instruction cache is disclosed. There are a number of tag memory banks. Each tag memory bank is associated with a unique instruction cache. Each tag memory bank has a number of tag memory rows and each tag memory row has a number of tag memory cells. Certain upper bits of a program counter are compared to a tag stored in one row of a tag memory bank. If there is a match between the certain upper bits of the program counter and the tag, a hit signal is generated. The hit signal indicates that the tag memory bank containing the matched row (i. e. the matched tag) is associated with the instruction cache having a desired instruction. The desired instruction is then read from the instruction cache associated with the tag memory bank corresponding to the generated hit signal. Thus, instead of reading one instruction from each of the instruction caches and then eliminating all but one of the read instructions, only the desired instruction from a single instruction cache is read. As such, a large amount of power is saved.

US Patent:

6684320, Jan 27, 2004

Filed:

Feb 28, 2002

Appl. No.:

10/085437

Inventors:

Moataz A Mohamed - Irvine CA
Chien-Wei Li - Mission Viejo CA
John R. Spence - Villa Park CA

Assignee:

Mindspeed Technologies, Inc. - Newport Beach CA

International Classification:

G06F 938

US Classification:

712 24, 712204, 712206, 712210, 712213, 712215

Abstract:

An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit.

US Patent:

7100022, Aug 29, 2006

Filed:

Feb 28, 2002

Appl. No.:

10/085724

Inventors:

Moataz Mohamed - Irvine CA, US
John Spence - Villa Park CA, US
Kevin R. Bowles - Mission Viejo CA, US
Chien-Wei Li - Urbana IL, US

Assignee:

Mindspeed Technologies, Inc. - Newport Beach CA

International Classification:

G06F 15/16
G06F 15/00

US Classification:

712 24, 712217

Abstract:

In one embodiment, move buses utilized in presently known VLIW processors are eliminated and replaced with a busing scheme which results in transfer of operands from each register file bank to any data path block while also reducing the total bus width and total power consumption associated with transport of operands from register file banks to data path blocks. According to this busing scheme, the speed of VLIW processor is also improved since the need for one clock cycle to move operands from one register file bank to another is overcome. In another embodiment, a scheduling restriction is used to eliminate the need for the presently required write back buses used by various data path blocks. In yet another embodiment, a scheduling restriction is imposed which results in a reduction of the number of ports, a reduction in the width of buses, and a reduction of power consumption.

US Patent:

7127588, Oct 24, 2006

Filed:

Dec 5, 2000

Appl. No.:

09/730039

Inventors:

Moataz A. Mohamed - Irvine CA, US
John R. Spence - Villa Park CA, US

Assignee:

Mindspeed Technologies, Inc. - Newport Beach CA

International Classification:

G06F 15/82

US Classification:

712 24

Abstract:

In one exemplary embodiment, the disclosed VLIW processor comprises a number of threads where each thread includes a processing unit. For example, there can be two threads, where each of the two threads has its own processing unit. According to this exemplary embodiment, a number of VLIW packets are divided into a number of issue groups. As an example, two VLIW packets are divided into two issue groups each. The first issue group in the first VLIW packet is provided to a first thread for execution in the first thread processing unit during a first clock cycle. Concurrently, the first issue group in the second VLIW packet is provided to a second thread for execution in the second thread processing unit during the same clock cycle, i. e. during the first clock cycle. Moreover, the second issue group in the first VLIW packet is provided to the first thread for execution in the first thread processing unit during a second clock cycle.

US Patent:

6104654, Aug 15, 2000

Filed:

Dec 20, 1999

Appl. No.:

9/467532

Inventors:

John R. Spence - Villa Park CA

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

G11C 700

US Classification:

365203

Abstract:

The invention's reference precharge circuit and bit line precharge circuits are comprised of two NFET transistors and one PFET transistor. In the preferred embodiment of the invention where the supply voltage is 3. 0 volts, the two NFET transistors result in a voltage drop of 2. 0 volts so as to produce a reference precharge signal or a bit line precharge signal having a voltage of 1. 0 volts. When a precharge enable signal is on, the PFET transistor is connected to ground and is barely on such that the path from the reference precharge signal or the bit line precharge signal to ground is a low impedance path. Moreover, the path from the reference precharge signal or the bit line precharge signal to the supply voltage is also of low impedance. Accordingly, the voltages present at the reference precharge signal or the bit line precharge signal are substantially noise free. The invention also utilizes a unique sense amp that quickly detects changes in the voltage level of a bit line in relation to the voltage level of the reference precharge signal.

US Patent:

40041638, Jan 18, 1977

Filed:

Mar 11, 1976

Appl. No.:

5/666116

Inventors:

John R. Spence - Villa Park CA

Assignee:

Rockwell International Corporation - El Segundo CA

International Classification:

H03K 513
H03K 1756

US Classification:

307293

Abstract:

A time delay circuit comprising an improved charge transfer scheme for use in a microelectronic circuit, such as, but not limited to, a calculator, and the like. The circuit efficiently charges a capacitance means with a signal to subsequently energize a utilization means. Sufficient time delay is provided when charging the capacitance means, after power is applied to the microelectronic chip means and before the utilization means is suitably energized, to insure that associated logic is first initialized and sources of reference potential are at proper operating levels.

US Patent:

54555426, Oct 3, 1995

Filed:

Nov 22, 1993

Appl. No.:

8/155500

Inventors:

John R. Spence - Villa Park CA
Rajiv Gupta - Brea CA
Ming M. Zhang - Irvine CA

Assignee:

Rockwell International Corporation - Seal Beach CA

International Classification:

H03B 530

US Classification:

331158

Abstract:

An oscillator circuit provides a symmetrical signal without halving the frequency of a crystal oscillator 12. The input 14 of the crystal oscillator 12 is low pass filtered, and the output 18 of the filter 16 is differential voltage compared with the input 14 of the crystal oscillator 12. The output 22 of the differential voltage comparator 20 is symmetrical and of the same frequency as the crystal oscillator 12. The crystal oscillator 12 is preferably a Pierce oscillator.