John M Stratton

US Patent:

8413151, Apr 2, 2013

Filed:

Dec 19, 2007

Appl. No.:

11/960652

Inventors:

John A. Stratton - Champaign IL, US
David Luebke - Charlottesville VA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 9/46
G06F 15/76

US Classification:

718102, 712 22

Abstract:

One embodiment of the present invention sets forth a technique for selectively spawning threads within a multiprocessing system. A computation work distributor (CWD), within the system, is responsible for performing the detailed work needed to spawn a thread grid. A request to the CWD to spawn a thread grid includes a predicate table, which includes an array of flags used to indicate which thread indices should have an associated thread block spawned and which should not. Greater efficiency is achieved by only spawning thread blocks that should perform useful computation.

US Patent:

8417735, Apr 9, 2013

Filed:

Dec 12, 2007

Appl. No.:

11/955313

Inventors:

John A. Stratton - Champaign IL, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 17/30

US Classification:

707803, 707758, 707791, 707801, 712220

Abstract:

One embodiment of the present invention sets forth a technique for performing a parallel scan operation with high computational efficiency in a single-instruction multiple-data (SIMD) environment. Each participating thread initially writes an extended region of a data array to initialize the region with an identity value. For example, a value of zero is used as the identity value for addition. The initialized region of the data array includes an initialized entry for every possible out of bounds index that may be computed in the normal course of the parallel scan operation. During the parallel scan operation each thread computes data array indices according to any technically appropriate technique. When a participating thread computes an index that would conventionally be out of bounds, the thread is able to retrieve an identity value from the initialized region of the data array rather than perform a bounds check that returns the identity value.

US Patent:

8615770, Dec 24, 2013

Filed:

Aug 29, 2008

Appl. No.:

12/202157

Inventors:

John A. Stratton - Champaign IL, US
David Luebke - Charlottesville VA, US

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06F 9/46

US Classification:

718107, 718100

Abstract:

One embodiment of the present invention sets forth a technique for partitioning a predecessor thread program into sub-programs and dynamically spawning a thread grid of the sub-programs based on the outcome of a conditional statement in the predecessor thread program. The programming instructions for the predecessor thread program are analyzed to assess the benefit of partitioning the thread program at a conditional statement into sub-programs. If the predecessor thread program is partitioned, then each branch of the conditional statement may be used to form a separate sub-program. Predicate tables are populated at the predecessor thread program run-time to establish which possible instances of the thread sub-programs should be spawned in subsequent execution phases.

Address:

906 Summerfield Pl, Lawrence, KS 66049

VIN:

2T1BR32E87C740792

Make:

TOYOTA

Model:

COROLLA

Year:

2007