John B Thayer

US Patent:

53414942, Aug 23, 1994

Filed:

Dec 10, 1993

Appl. No.:

8/165514

Inventors:

John S. Thayer - Houston TX
Dale J. Mayer - Houston TX
Javier F. Izquierdo - Houston TX
Paul R. Culley - Cypress TX
John A. Landry - Tomball TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1206

US Classification:

395425

Abstract:

A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.

US Patent:

62984381, Oct 2, 2001

Filed:

May 3, 1999

Appl. No.:

9/303513

Inventors:

John S. Thayer - Houston TX
John G. Favor - Scotts Valley CA
Frederick D. Weber - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Compaq Computer Corporation - Houston TX

International Classification:

G06F 738
G06F 900
G06F 944

US Classification:

712226

Abstract:

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

US Patent:

60615214, May 9, 2000

Filed:

Dec 2, 1996

Appl. No.:

8/759042

Inventors:

John S. Thayer - Houston TX
Gary W. Thome - Tomball TX
John G. Favor - Scotts Valley CA
Frederick D. Weber - San Jose CA

Assignee:

Compaq Computer Corp. - Houston TX
Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 9302

US Classification:

39580009

Abstract:

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU may be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers may be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands. In one embodiment, an arithmetic logic unit may be partitioned into at least two logic portions.

US Patent:

61733660, Jan 9, 2001

Filed:

Dec 2, 1996

Appl. No.:

8/759044

Inventors:

John S. Thayer - Houston TX
John G. Favor - Scotts Valley CA
Frederick D. Weber - San Jose CA

Assignee:

Compaq Computer Corp. - Houston TX
Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1204

US Classification:

711129

Abstract:

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

US Patent:

52261220, Jul 6, 1993

Filed:

Aug 21, 1987

Appl. No.:

7/088093

Inventors:

John S. Thayer - Spring TX
Montgomery C. McGraw - Spring TX

Assignee:

Compaq Computer Corp. - Houston TX

International Classification:

G06F 1516

US Classification:

395275

Abstract:

A system utilizes one or more programmable logic arrays or gate arrays for regulating the commands available to a microprocessor, and intercepting certain of those commands according to predetermined citeria. The system selects and processes designated commands relating to the FORCE-A20 signal and CPU-RESET signal for a keyboard controller functionally attached to an INTEL 80286 or 80386 microprocessor. The system includes one or more programmable logic arrays or gate arrays for allowing all input commands to pass directly through to the keyboard controller except the command sequence relating to the FORCE-A20 signal or the CPU-RESET signal.

US Patent:

58019758, Sep 1, 1998

Filed:

Dec 2, 1996

Appl. No.:

8/759045

Inventors:

John S. Thayer - Houston TX
John G. Favor - Scotts Valley CA
Frederick D. Weber - San Jose CA

Assignee:

Compaq Computer Corporation and Advanced Micro Devices, Inc.

International Classification:

G06F 1714

US Classification:

36472503

Abstract:

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

US Patent:

61416738, Oct 31, 2000

Filed:

May 25, 1999

Appl. No.:

9/318671

Inventors:

John S. Thayer - Houston TX
John Gregory Favor - Scotts Valley CA
Frederick D. Weber - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Compaq Computer Corp. - Houston TX

International Classification:

G06F 1714

US Classification:

708402

Abstract:

A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector registers, a vector arithmetic logic unit (ALU), and an operand routing unit (ORU) to perform a maximum number of the multimedia operations within as few instruction cycles as possible. Complex algorithms are readily performed by arranging operands upon the vector ALU in accordance with the desired algorithm flowgraph. The ORU aligns the operands within partitioned slots or sub-slots of the vector registers using vector instructions unique to the MEU. At the output of the ORU, operand pairs from vector source or destination registers can be easily routed and combined at the vector ALU. The vector instructions employ special load/store instructions in combination with numerous operational instructions to carry out concurrent multimedia operations on the aligned operands.

US Patent:

59318929, Aug 3, 1999

Filed:

Dec 20, 1996

Appl. No.:

8/770842

Inventors:

Gary W. Thome - Tomball TX
John S. Thayer - Houston TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1710
G06F 1500

US Classification:

708322

Abstract:

A signal represented as a matrix of input values is adaptively filtered using a processor with a multimedia extension unit. A plurality of coefficients are loaded into a first vector register and input values are loaded into a second vector register. Next, for each of the coefficients in the first vector register, (1) a single cycle vector multiply-accumulate operation is performed between the selected coefficient and the input values stored in the second vector register and the result is stored in a third register; (2) a partition-shift on input values in the second vector register is then performed and a new input value is then moved into the second vector register. After each of the four loaded coefficients have been processed, the results are saved and the operation is repeated until all input values in the matrix have been processed.