John K Tse from 17 Bradford, Irvine, CA 92602, age 53, Phone: 7147347968

Integrated Circuit Reconfiguration Techniques
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US Patent:

8183883, May 22, 2012
Filed:

Apr 16, 2010
Appl. No.:

12/762295
Inventors:

Chee Seng Tan - Tarman Tanjung, MY
Chai Sia Tan - Bukit Gambir, MY
Elden Chau - San Jose CA, US
John Tse - San Jose CA, US
Neville Carvalho - Campbell CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

H03K 19/177
G06F 7/38
US Classification:

326 39, 326 41, 710 13
Abstract:

A memory configuration circuit is provided. The memory configuration circuit may be integrated into a programmable logic device (PLD) and as such, may be used to configure and reconfigure specific elements in the PLD. The memory configuration circuit includes a comparator circuit and a counter. The comparator circuit is coupled to receive two data words from two different memory configuration sources. The comparator circuit compares the two data words received before writing one of the data words to a configuration memory. One of the data words may be written to the configuration memory if the two data words compared are not equal. The counter increments the address of the memory configuration sources so that a next data word can be processed after the current data word is processed.

Method And Apparatus For Circuit Block Reconfiguration Eda
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US Patent:

8595670, Nov 26, 2013
Filed:

Mar 8, 2010
Appl. No.:

12/719298
Inventors:

John Tse - San Jose CA, US
Neville Carvalho - Campbell CA, US
Assignee:

Altera Corporation - San Jose CA
International Classification:

G06F 17/50
US Classification:

716116, 716100, 716103, 716104, 716117
Abstract:

Methods and apparatus are described for efficiently performing EDA processing to arrive at a hardware definition for a varying fraction of a large circuit design. EDA processing is conducted targeting a pseudo hardware device with sufficient capacity to embody circuitry for the varying fraction, but substantially less than the true hardware target. The novel methods and apparatus may be beneficially employed to produce reconfiguration information for circuits that include programmable logic, for example.

Hierarchical Circuit Partitioning Using Sliding Windows
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US Patent:

6301694, Oct 9, 2001
Filed:

Sep 24, 1997
Appl. No.:

8/936112
Inventors:

Fung Fung Lee - Milpitas CA
John Tse - El Cerrito CA
Assignee:

Altera Corporation - San Jose CA
International Classification:

G06F 1750
US Classification:

716 11
Abstract:

Systems and methods of hierarchical circuit partitioning are provided. More specifically, the invention utilizes a sliding window which is moved over portions of a hierarchical structure representing a programmable logic device. The window includes some but not all containers of the hierarchical structure so that logic cells may be partitioned within the window. After the logic cells are partitioned in the window, the window is moved to a different location of the hierarchical structure. By utilizing a sliding window, the invention is able to recursively partition logic cells into portions of the hierarchical structure which increases the overall efficiency of the partitioning.

Dual Function Antenna
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US Patent:

42452228, Jan 13, 1981
Filed:

Sep 15, 1978
Appl. No.:

5/942859
Inventors:

Edward Eng - San Jose CA
Glen D. Gibbons - San Jose CA
David L. Thomas - Mountain View CA
John W. Tse - Sunnyvale CA
Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC
International Classification:

H01Q 128
US Classification:

343708
Abstract:

A dual function antenna operating at two frequency bands for both the radar uzing function and the telemetry function with a single antenna cavity. A pair of flush-mounted, cavity-backed circumferential slots are located near the base of a missile body and are fed out-of-phase to produce an N=1 mode gain pattern with peaks at nose-on and aft aspects. Each slot is excited by a probe and tee-bar transition. A telemetry band trap circuit is incorporated into the radar band probe and tee-bar to isolate telemetry band energy. A single telemetry probe is inserted into the cavity and spaced apart from the radar probe to excite the antenna at telemetry frequencies.

Programmable Logic Array Integrated Circuit Devices With Flexible Carry Chains
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US Patent:

56315767, May 20, 1997
Filed:

Sep 1, 1995
Appl. No.:

8/522554
Inventors:

Fung F. Lee - Milpitas CA
John Tse - El Cerrito CA
Assignee:

Altera Corporation - San Jose CA
International Classification:

H03K 19177
US Classification:

326 39
Abstract:

A programmable logic array integrated circuit has a plurality of logic modules, each of which is programmable to perform any of several logic functions. One such function is the performance of one place of binary addition yielding a sum out signal and a carry out signal. In addition to a dedicated carry chain which conveys the carry out signal of each logic module to the carry in input of another predetermined logic module, circuitry is provided for allowing the carry out signal of each logic module to be alternatively routed through the more general interconnection circuitry of the device. This increases the flexibility of routing of the carry out signals, thereby increasing the flexibility of use of the integrated circuit. Improved circuitry for handling a carry in signal may also be provided in each logic module.