John Y Tse

US Patent:

62126687, Apr 3, 2001

Filed:

May 27, 1997

Appl. No.:

8/863880

Inventors:

John Tse - El Cerrito CA
Fung Fung Lee - Milpitas CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1750

US Classification:

716 7

Abstract:

A method for partitioning a group of cells in a network into a set of disjoint blocks of cells. The network is represented by a hierarchical graph with each level representing a hierarchy of resources, leaf nodes representing the blocks of cells, and edges representing interconnections between resources. A gain matrix is formed by combining a gain vector for each level of hierarchy for each possible move. Cells are moved between leaf nodes based on the gain matrix computed.

US Patent:

61029645, Aug 15, 2000

Filed:

Oct 27, 1997

Appl. No.:

8/958436

Inventors:

John Tse - El Cerrito CA
Fung Fung Lee - Milpitas CA
David Wolk Mendel - Sunnyvale CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1750

US Classification:

716 18

Abstract:

A technique is disclosed for efficiently placing logic cells from an electronic design during an incremental recompile. This is accomplished by fixing in place as many logic cells as possible during the recompile procedure. To understand how this works, recognize than an "original electronic design" has already been fully compiled. Now, a user has made one or more changes to the original electronic design to produce a "changed electronic design. " The disclosed technique fits the changed electronic design, during incremental recompile, without effecting too much of the logic previously fit during compilation of the original electronic design. Initially, a compiler attempts to fit logic cells of the changed portion of the electronic design onto available logic elements of the hardware device while confining logic cells from the unchanged portion of the changed electronic design to their original positions. If this fails, the compiler allows logic cells from the unchanged portion of the changed electronic design to shift by a limited amount to other logic elements within the target hardware device. At first, this shifting is fairly constrained in order to preserve as much of the original compilation's placement as possible.

US Patent:

56597177, Aug 19, 1997

Filed:

Jul 31, 1995

Appl. No.:

8/508401

Inventors:

John Tse - El Cerrito CA
David W. Mendel - Sunnyvale CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 1750

US Classification:

395500

Abstract:

Improved circuit partitioning methods are provided which combine the advantage of multiple starting positions of the random initial placement approach with the advantage of optimal starting positions of the greedy initial placement approach, by starting with greedy initial placement and modifying partitioning constraints on subsequent passes so that each pass begins in a new position, In addition, the partitioning goals of interconnection minimization and resource utilization efficiency may be prioritized according to a design goal by manipulating the manner in which partitioning constraints are changed during each partitioning pass. Furthermore a user may adjust the weight of the benefits for eliminating existing interconnections and the weight of the penalties for adding new interconnections in accordance with a design goal.