John David Wellman

US Patent:

20070050592, Mar 1, 2007

Filed:

Aug 31, 2005

Appl. No.:

11/216659

Inventors:

Michael Gschwind - Chappaqua NY, US
John Wellman - Hopewell Junction NY, US

International Classification:

G06F 12/00
G06F 13/00

US Classification:

711201000, 711154000

Abstract:

One embodiment of the present method and apparatus for accessing misaligned data streams includes receiving a data request, where the data request includes a request for misaligned data, and retrieving at least a portion of the requested data from a data stream buffer associated with the data stream. If the data retrieved from the data stream buffer does not comprise all of the requested data, the remainder of the requested data is retrieved from memory and combined with the data stream buffer data. In this manner, the number of memory accesses necessary to retrieve the requested misaligned data is reduced. Additional embodiments of the present invention include mechanisms for ensuring data coherence with respect to write updates and protocol requests. Moreover, the present invention advantageously reduces the need for pipeline upset events/pipeline hazards that typically result in performance degradation in pipelined microprocessors.

US Patent:

20080263325, Oct 23, 2008

Filed:

Apr 19, 2007

Appl. No.:

11/737491

Inventors:

Prabhakar Kudva - New York NY, US
David S. Levitan - Austin TX, US
Balaram Sinharoy - Poughkeepsie NY, US
John D. Wellman - Hopewell Junction NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 9/30

US Classification:

712203

Abstract:

A microprocessor and system with improved performance and power in simultaneous multithreading (SMT) microprocessor architecture. The microprocessor and system includes a process wherein the processor has the ability to select instructions from one thread or another in any given processor clock cycle. Instructions from each, thread may be assigned selection priorities at multiple decision points in a processor in a given cycle dynamically. The thread priority is based on monitoring performance behavior and activities in the processor. In the exemplary embodiment, the present invention discloses a microprocessor and system for synchronizing thread priorities among multiple decision points throughout the micro-architecture of the microprocessor. This system and method for synchronizing thread priorities allows each thread priority to he in sync and aware of the status of other thread priorities at various decision points within the microprocessor.