John Z Zhu

US Patent:

20020067831, Jun 6, 2002

Filed:

Apr 24, 2001

Appl. No.:

09/840954

Inventors:

John Zhu - San Diego CA, US
Michele Jannette - Cardiff CA, US

Assignee:

SONY CORPORATION - Tokyo

International Classification:

H04K001/00

US Classification:

380/272000, 380/270000

Abstract:

A wireless broadband IP network with a data transfer rate in excess of one megabyte per second for providing up to the minute subscription services to mobile client devices. The network has a network operation center (NOC) and base stations communicating with respective data centers and with mobile client devices. As a mobile client device moves from the area of one base station to another, the provision of subscription services to the device is handed off from one base station to the next without interruption.

US Patent:

20020174175, Nov 21, 2002

Filed:

Apr 23, 2001

Appl. No.:

09/840328

Inventors:

John Zhu - San Diego CA, US
Michele Jannette - Cardiff CA, US

Assignee:

SONY CORPORATION - Tokyo

International Classification:

G06F015/16

US Classification:

709/203000

Abstract:

A wireless broadband IP network with a data transfer rate in excess of one megabyte per second for providing up to the minute subscription services to mobile client devices. The network has a network operation center (NOC) and base stations communicating with the NOC. Foreign agents at the base station communicate with a home agent at the NOC to identify client devices and grant client devices access to subscription services based on information stored at the NOC.

US Patent:

20140001568, Jan 2, 2014

Filed:

Nov 21, 2012

Appl. No.:

13/684107

Inventors:

John J. Zhu - San Diego CA, US
Xia Li - San Diego CA, US

Assignee:

QUALCOMM INCORPORATED - San Diego CA

International Classification:

H01L 27/112
H01L 21/8239

US Classification:

257379, 438382

Abstract:

One feature pertains to an integrated circuit, comprising an access transistor and an antifuse. The access transistor includes at least one source/drain region, and the antifuse has a conductor-insulator-conductor structure. The antifuse includes a first conductor that acts as a first electrode, and also includes an antifuse dielectric, and a second conductor. A first surface of the first electrode is coupled to a first surface of the antifuse dielectric, a second surface of the antifuse dielectric is coupled to a first surface of the second conductor. The second conductor is electrically coupled to the access transistor's source/drain region. The antifuse is adapted to transition from an open circuit state to a closed circuit state if a programming voltage Vgreater than or equal to an antifuse dielectric breakdown voltage is applied between the first electrode and the second conductor.

US Patent:

20140070364, Mar 13, 2014

Filed:

Sep 13, 2012

Appl. No.:

13/613008

Inventors:

Yong Park - San Diego CA, US
Zhongze Wang - San Diego CA, US
John J. Zhu - San Diego CA, US
Choh Fei Yeap - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H01L 23/525

US Classification:

257530, 438600

Abstract:

An electrically programmable gate oxide anti-fuse device includes an anti-fuse aperture having anti-fuse links that include metallic and/or semiconductor electrodes with a dielectric layer in between. The dielectric layer may be an interlayer dielectric (ILD), an intermetal dielectric (IMD) or an etch stop layer. The anti-fuse device may includes a semiconductor substrate having a conductive gate (e.g., a high K metal gate) disposed on a surface of the substrate, and a dielectric layer disposed on the conductive gate. A stacked contact can be disposed on the dielectric layer and a gate contact is disposed on an exposed portion of the gate.

US Patent:

20220336607, Oct 20, 2022

Filed:

Apr 20, 2021

Appl. No.:

17/235491

Inventors:

- San Diego CA, US
John Jianhong ZHU - San Diego CA, US
Giridhar NALLAPATI - San Diego CA, US

International Classification:

H01L 29/423
H01L 21/8234
H01L 29/66
H01L 29/417
H01L 27/088

Abstract:

Disclosed are apparatuses including a transistor cell and methods of fabricating the transistor cell. The transistor cell may include a substrate, an active region and a gate having a gate contact in the active region. The transistor cell may further include a first portion of a spacer of the gate contact formed from a first material, and a second portion of the spacer of the gate contact formed from a second material.

US Patent:

20220262723, Aug 18, 2022

Filed:

Feb 16, 2021

Appl. No.:

17/176969

Inventors:

- San Diego CA, US
John Jianhong ZHU - San Diego CA, US
Haining YANG - San Diego CA, US

International Classification:

H01L 23/522
H01L 23/532
H01L 23/528
H01L 21/768

Abstract:

An integrated circuit (IC) having an interconnect structure with metal lines with different conductive materials for different widths and a method for fabricating such an IC. An example IC generally includes an active layer and an interconnect structure disposed thereabove and comprising a plurality of metal layers and one or more vias landing on metal lines. At least one of the plurality of metal layers comprises one or more first metal lines and one or more second metal lines. The one or more first metal lines have one or more first widths and comprise a first conductive material including copper. The one or more second metal lines have one or more second widths and comprise a second conductive material different from the first conductive material, where the second widths are narrower than the first widths. The vias have one or more third widths and comprise a third conductive material.

US Patent:

20210320059, Oct 14, 2021

Filed:

Apr 13, 2020

Appl. No.:

16/846591

Inventors:

- San Diego CA, US
John Jianhong ZHU - San Diego CA, US
Lixin GE - San Diego CA, US

International Classification:

H01L 23/522
H01L 49/02
H01L 23/528

Abstract:

Certain aspects of the present disclosure generally relate to a hybrid back-end-of-line (BEOL) dielectric for a high capacitance density metal-oxide-metal (MOM) capacitor, especially in lower BEOL layers. One example semiconductor device includes an active layer and a first metal layer disposed above the active layer. The first metal layer generally includes: a first electrode; a second electrode, wherein the first and second electrodes have interdigitated fingers; a first dielectric material disposed at least partially between at least two adjacent fingers of the first and second electrodes; and a second dielectric material, wherein the second dielectric material is different from the first dielectric material and wherein the first electrode, the second electrode, and the first dielectric material compose a portion of a metal-oxide-metal (MOM) capacitor.

US Patent:

20210320175, Oct 14, 2021

Filed:

Apr 9, 2020

Appl. No.:

16/844699

Inventors:

- San Diego CA, US
John Jianhong ZHU - San Diego CA, US

International Classification:

H01L 29/08
H01L 27/092
H01L 29/78
H01L 29/66

Abstract:

The parasitic capacitance of a transistor may be reduced by mismatching the source and drain. Faster low finger count transistors may be achieved with lower drain capacitance and a frequency gain on the D1 inverter as described for the examples herein. In one such example, a transistor includes a source and a drain wherein a length of the source is more than a length of the drain, a width of the source is more than a width of the drain, or a height of the source is more than a height of the drain.