Jon Powell

US Patent:

46851283, Aug 4, 1987

Filed:

Dec 24, 1984

Appl. No.:

6/686314

Inventors:

Jon N. Powell - Lewisville TX

Assignee:

Thomson Components-Mostek Corp. - Carrollton TX

International Classification:

H04Q 342

US Classification:

379272

Abstract:

An address (n) is associated with a sort element (30) so that input signals are compared with each other, or with the address (n) in the case of a null input (N). Several elements (30) are interconnected to provide unique signal routing from any input to a particular output, depending upon a characteristic of an input signal itself without reference to other input signals.

US Patent:

48357332, May 30, 1989

Filed:

Sep 30, 1985

Appl. No.:

6/781584

Inventors:

Jon Powell - Lewisville TX

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

G06F 1200
G06F 1206

US Classification:

364900

Abstract:

An integrated circuit memory includes processing capability on the same chip, on one or both of an address path and data path between a set of access registers and a memory array so that an address can be generated, checked or manipulated and/or data can be manipulated or compared with a reference pattern of data.

US Patent:

47589817, Jul 19, 1988

Filed:

Dec 24, 1984

Appl. No.:

6/686180

Inventors:

Jon N. Powell - Lewisville TX

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

G06F 708

US Classification:

364900

Abstract:

A circuit element incorporating a logic circuit and a constant address number signal source which serves distinguish one circuit element from others that are otherwise similar, has two inputs (A) and (B), a low output (L) and a high output (H). This element utilizes the address portions of respective digital signal bytes provided respectively to its two outputs, to determine whether the A input will go to the low output and the B input to the high output or vice versa. The element includes, in addition to the address source, a detector for null address portions at each output and a switch responsive to the null detector for substituting the internally stored address number for the input address when a null address portion is detected. The logic circuit also includes an equality detector, for comparing the outputs of the respective switches, which cooperates with the null detector for the A input and an AND-gate to produce a control signal when the switch outputs are equal and the null detector for the A input detects a null address portion. Another comparator produces a control signal when the output of the switch controlled by the A input is greater than the output of the other switch.