Jon P Slaughter

US Patent:

8228715, Jul 24, 2012

Filed:

May 28, 2010

Appl. No.:

12/789838

Inventors:

Thomas Andre - Austin TX, US
Saied Tehrani - Paradise Valley AZ, US
Jon Slaughter - Tempe AZ, US
Nicholas Rizzo - Gilbert AZ, US

Assignee:

Everspin Technologies, Inc. - Chandler AZ

International Classification:

G11C 11/00
G11C 11/14

US Classification:

365158, 365148, 365171

Abstract:

An apparatus and method of programming a spin-torque magnetoresistive memory array includes a metal reset line positioned near each of a plurality of magnetoresistive bits and configured to set the plurality of magnetoresistive memory elements to a known state by generating a magnetic field when an electrical current flows through it. A spin torque transfer current is then applied to selected ones of the magnetoresistive bits to switch the selected bit to a programmed state. In another mode of operation, a resistance of the plurality of bits is sensed prior to generating the magnetic field. The resistance is again sensed after the magnetic field is generated and the data represented by the initial state of each bit is determined from the resistance change. A spin torque transfer current is then applied only to those magnetoresistive bits having a resistance different from prior to the magnetic field being applied.

US Patent:

20190156878, May 23, 2019

Filed:

Dec 12, 2018

Appl. No.:

16/217185

Inventors:

- Chandler AZ, US
Syed M. ALAM - Austin TX, US
Jon SLAUGHTER - Slingerlands NY, US
Chitra SUBRAMANIAN - Mahopac NY, US

Assignee:

EVERSPIN TECHNOLOGIES, INC. - Chandler AZ

International Classification:

G11C 11/16

Abstract:

A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

US Patent:

20170263300, Sep 14, 2017

Filed:

May 25, 2017

Appl. No.:

15/605508

Inventors:

- Chandler AZ, US
Syed M. ALAM - Austin TX, US
Jon SLAUGHTER - Chandler AZ, US
Chitra SUBRAMANIAN - Mahopac NY, US

Assignee:

EVERSPIN TECHNOLOGIES, INC. - Chandler AZ

International Classification:

G11C 11/16
G06F 12/0804

Abstract:

A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

US Patent:

20160093349, Mar 31, 2016

Filed:

Sep 30, 2014

Appl. No.:

14/502367

Inventors:

- Chandler AZ, US
Syed M. Alam - Austin TX, US
Jon Slaughter - Tempe AZ, US
Chitra Subramanian - Mahopac NY, US

International Classification:

G11C 11/16

Abstract:

A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.