Jonathan J Chen

US Patent:

6934867, Aug 23, 2005

Filed:

May 17, 2002

Appl. No.:

10/150231

Inventors:

Jonathan Y. Chen - Yorktown Heights NY, US
Patrick J. Meaney - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F001/04

US Classification:

713401, 713503

Abstract:

A method of calibrating an interface is provided to automatically achieve a minimal cycle latency while maintaining synchronous data arrival between a multiplicity of self-aligning interfaces. Independent self-alignment interfaces may de-skew data bits and have them arrive on a minimum cycle boundary. However, if all the interfaces do not arrive on the same cycle, SMP designs may not function properly. For instance, with a single control chip and multiple data chips on an AMP node, the control chip often sends out controls to the dataflow chips. If the data arriving on the elastic interfaces is not synchronized with the controls, the data is not routed properly. The method employs a calibration pattern to determine the latest cycle that data is received across the elastic interfaces and calculates the target cycle for all the interfaces to match this latest cycle. The target cycle is fed back into the design and the data is received synchronously, also provided is a test to ensure that the data arrives synchronously.

US Patent:

6954870, Oct 11, 2005

Filed:

Mar 12, 2002

Appl. No.:

10/096382

Inventors:

Jonathan Y. Chen - Yorktown Heights NY, US
Frank D. Ferraiolo - Essex Junction VT, US
Kevin C. Gower - LaGrangeville NY, US
Patrick J. Meaney - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F001/12

US Classification:

713401

Abstract:

A method of calibrating an elastic interface is provided to automatically achieve a minimal cycle delay through the interface. An existing self-alignment interface (i. e. elastic interface) is used to de-skew within a cycle and stage the data to have it arrive on a given, programmed target cycle. However, this target cycle must be calculated in advance and may be larger than it needs to be, causing more latency on the interface. This method is used to determine the earliest target cycle (with or without additional guard-band). This target cycle is used to adjust the interface automatically to achieve this earliest target cycle. The determination of earliest target cycle can be done once, continuously, or using a sample window. The method also can be used for interfaces that have frequency multipliers or phase shifts at its boundaries.

US Patent:

20020144189, Oct 3, 2002

Filed:

Apr 2, 2001

Appl. No.:

09/824389

Inventors:

Jonathan Chen - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F011/00

US Classification:

714/043000, 714/044000

Abstract:

An automatic delay detection and receiver adjustment method for a synchronous communications bus system sends a test pattern to the receivers of the system during a detection phase, uses the test pattern to determine a longest delay time for each bus line, and adjusts a receiver for each bit line to receive incoming signals at a time based on the determined longest delay time.