Jonathan S Chu

US Patent:

7082595, Jul 25, 2006

Filed:

Feb 11, 2005

Appl. No.:

11/055905

Inventors:

Jonathan Chu - Poughkeepsie NY, US
George D. Gristede - Katonah NY, US
Gregory A. Northrop - Putnam Valley NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 18, 716 8, 716 9, 716 10

Abstract:

A physical device layout tool and method. The method and tool receive a user provided schematic with circuit data and placement parameters, including defaults. Further inputs include a definition of cell physical position in the horizontal direction, a definition of the cell's vertical stacking level, a definition of the cell orientation, a specification of vertical alignment of multiple cell instances, and a definition of vertical spacing between 2 adjacent cell instances. These input parameters are used to generate a layout with the placed circuit elements.

US Patent:

7228514, Jun 5, 2007

Filed:

Jan 21, 2005

Appl. No.:

11/040139

Inventors:

Jonathan M. Chu - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 5, 716 4

Abstract:

A circuit design technique is provided for automatically estimating lengths of interconnect segments to be employed in interconnecting at least some circuit components of a plurality of placed circuit components of a circuit layout. The automatically estimating includes automatically generating pin locations for a plurality of pins in at least one level of the hierarchy to be employed with the at least some circuit components of the circuit layout, wherein the interconnect segments interconnect the plurality of pins. A route estimator is employed to estimate lengths of the interconnect segments based on the pin locations of the plurality of pins. The estimated interconnect segment lengths are then employed in automatically estimating resistance capacitance interconnect parasitics for the interconnect segments to be employed in the circuit layout.