Jonathan W Clark

US Patent:

20220285334, Sep 8, 2022

Filed:

May 24, 2022

Appl. No.:

17/664841

Inventors:

- Camarillo CA, US
Jonathan Clark - Camarillo CA, US

Assignee:

Semtech Corporation - Camarillo CA

International Classification:

H01L 25/00
H01L 23/00
H01L 23/60
H01L 23/495
H01L 21/768
H01L 25/065

Abstract:

A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.

US Patent:

20200286884, Sep 10, 2020

Filed:

May 20, 2020

Appl. No.:

16/878863

Inventors:

- Camarillo CA, US
William A. Russell - Thousand Oaks CA, US
Jonathan Clark - Camarillo CA, US

Assignee:

Semtech Corporation - Camarillo CA

International Classification:

H01L 27/02
H02H 9/04
H01L 29/861
H01C 7/12
H01L 23/62
H02H 9/02

Abstract:

A semiconductor device is protected from electrical overstress (EOS) and electro-static discharge (ESD) events by a series protection circuit electrically coupled in series along the transmission line between a signal source and a load. The series protection circuit includes a first field-effect transistor (FET) electrically coupled in series between the signal source and load. A parallel protection circuit is electrically coupled between the transmission line and a ground node. The parallel protection circuit can include a transient-voltage-suppression (TVS) diode.

US Patent:

20190355689, Nov 21, 2019

Filed:

Jul 29, 2019

Appl. No.:

16/525193

Inventors:

- Camarillo CA, US
Jonathan Clark - Camarillo CA, US
John MacLeod - Invergordon, GB

Assignee:

Semtech Corporation - Camarillo CA

International Classification:

H01L 23/00
H01L 23/31
H01L 21/02
H01L 21/683
H01L 21/56
H01L 21/78
H01L 23/498

Abstract:

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

US Patent:

20180286854, Oct 4, 2018

Filed:

Mar 19, 2018

Appl. No.:

15/925569

Inventors:

- Camarillo CA, US
William A. Russell - Thousand Oaks CA, US
Jonathan Clark - Camarillo CA, US

Assignee:

Semtech Corporation - Camarillo CA

International Classification:

H01L 27/02
H01L 23/62
H01L 29/861
H01C 7/12
H02H 9/04

Abstract:

A semiconductor device is protected from electrical overstress (EOS) and electro-static discharge (ESD) events by a series protection circuit electrically coupled in series along the transmission line between a signal source and a load. The series protection circuit includes a first field-effect transistor (FET) electrically coupled in series between the signal source and load. A parallel protection circuit is electrically coupled between the transmission line and a ground node. The parallel protection circuit can include a transient-voltage-suppression (TVS) diode.

US Patent:

20180102356, Apr 12, 2018

Filed:

Sep 29, 2017

Appl. No.:

15/721488

Inventors:

- Camarillo CA, US
Jonathan Clark - Camarillo CA, US
William A. Russell - Thousand Oaks CA, US

Assignee:

Semtech Corporation - Camarillo CA

International Classification:

H01L 27/02
H01L 25/16
H01L 29/864
H01L 49/02

Abstract:

A semiconductor device includes a semiconductor die. A transient voltage suppression (TVS) structure is formed in the semiconductor die. A capacitor is formed over the semiconductor die. In one embodiment, the capacitor is formed by depositing a first conductive layer over the semiconductor die, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the semiconductor die. In another embodiment, the capacitor is formed by forming a trench in the semiconductor die, depositing an insulating material in the trench, and depositing a conductive material in the trench.

US Patent:

20180047688, Feb 15, 2018

Filed:

Aug 4, 2017

Appl. No.:

15/668969

Inventors:

- Camarillo CA, US
Jonathan Clark - Camarillo CA, US
John MacLeod - Invergordon, GB

Assignee:

Semtech Corporation - Camarillo CA

International Classification:

H01L 23/00
H01L 23/498
H01L 21/02
H01L 21/56

Abstract:

A semiconductor device includes a semiconductor wafer. A plurality of pillar bumps is formed over the semiconductor wafer. A solder is deposited over the pillar bumps. The semiconductor wafer is singulated into a plurality of semiconductor die after forming the pillar bumps while the semiconductor wafer is on a carrier. An encapsulant is deposited around the semiconductor die and pillar bumps while the semiconductor die remains on the carrier. The encapsulant covers an active surface of the semiconductor die between the pillar bumps.

US Patent:

20170250172, Aug 31, 2017

Filed:

Feb 13, 2017

Appl. No.:

15/431528

Inventors:

- Camarillo CA, US
Jonathan Clark - Camarillo CA, US

Assignee:

Semtech Corporation - Camarillo CA

International Classification:

H01L 25/00
H01L 27/02
H01L 23/00
H01L 21/78
H01L 25/065
H01L 21/768

Abstract:

A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.