Jonathan S Combs

US Patent:

7552254, Jun 23, 2009

Filed:

Jul 30, 2003

Appl. No.:

10/630286

Inventors:

Robert T. George - Austin TX, US
Jason W. Brandt - Austin TX, US
Jonathan D. Combs - Austin TX, US
Peter J. Ruscito - Folsom CA, US
Sanjoy K. Mondal - San Marcos TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 3/00
G06F 12/00
G06F 9/26
G06F 13/00

US Classification:

710 58, 710 52, 710 55, 711169, 711205, 711206, 711207, 711208, 711209

Abstract:

In one embodiment of the present invention, an apparatus includes a pipeline resource having different address spaces each corresponding to a different address space identifier. Each address space may have entries that include data values associated with the address space identifier.

US Patent:

7783871, Aug 24, 2010

Filed:

Jun 30, 2003

Appl. No.:

10/609814

Inventors:

Jonathan D. Combs - Austin TX, US
Hoichi Cheong - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/00

US Classification:

712239

Abstract:

According to one embodiment a computer system is disclosed. The computer system includes a microprocessor and a chipset coupled to the microprocessor. The microprocessor removes stale branch instructions prior to the execution of a first cache line by finding existing branch prediction data for the first cache line.

US Patent:

8225046, Jul 17, 2012

Filed:

Sep 29, 2006

Appl. No.:

11/541174

Inventors:

Martin Licht - Round Rock TX, US
Jonathan Combs - Austin TX, US
Andrew Huang - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28
G06F 1/26
G06F 1/32

US Classification:

711128, 713320

Abstract:

A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to track consecutive misses to ways of a cache, i. e. hits/reads to other ways of cache. Based on the usage of ways and the non-usage of other ways, the way predicting logic determines if a way is to be powered down. In response to determining a way is to be powered down, the way predicting logic generates a power signal to power down an associated. Furthermore, upon a subsequent hit to a powered down way, the way predicting logic toggles the power signal to power up the associated way to ensure performance.

US Patent:

20050071518, Mar 31, 2005

Filed:

Sep 30, 2003

Appl. No.:

10/677039

Inventors:

Nicholas Samra - Austin TX, US
Stephan Jourdan - Portland OR, US
Jonathan Combs - Austin TX, US
Avinash Sodani - Hillsboro OR, US
Per Hammarlund - Hillsboro OR, US
Michael Cornaby - Hillsboro OR, US

International Classification:

G06F003/00

US Classification:

710001000

Abstract:

According to an embodiment of the invention, a method and apparatus for flag value renaming. An embodiment of a method comprises setting a flag for a processor via a first instruction, the first instruction being either a direct update instruction or an indirect update instruction; if the setting of the flag is by a direct update instruction, executing a succeeding second instruction that reads the flag prior to completion of the first instruction; and if the setting of the flag is by an indirect update instruction, delaying the second instruction until after completion of the first instruction.

US Patent:

20120079237, Mar 29, 2012

Filed:

Sep 24, 2010

Appl. No.:

12/890335

Inventors:

Jonathan D. Combs - Austin TX, US
Kameswar Subramaniam - Austin TX, US

International Classification:

G06F 9/22
G06F 9/30

US Classification:

712 32, 712211, 712E09004

Abstract:

An apparatus of one aspect includes a microcode storage, a microcode subroutine stored in the microcode storage, and a microcode caller of the microcode subroutine stored in the microcode storage. The microcode caller has a save microinstruction that indicates a destination storage location. The apparatus also includes microcode alias locations. Each of the microcode alias locations is operable to store a value. The value in the microcode alias location corresponds to a parameter passed between the microcode caller and the microcode subroutine. The apparatus includes save logic coupled with the microcode alias locations to receive the values from the microcode alias locations. The save logic is operable, responsive to the save microinstruction, to save the values from the microcode alias locations in the destination storage location indicated by the save microinstruction.

US Patent:

20120079248, Mar 29, 2012

Filed:

Sep 24, 2010

Appl. No.:

12/890292

Inventors:

Jonathan D. Combs - Austin TX, US
Kameswar Subramaniam - Austin TX, US
Jason Brandt - Austin TX, US

International Classification:

G06F 9/30
G06F 9/22

US Classification:

712211, 712E09004

Abstract:

An apparatus of an aspect includes a plurality of microcode alias locations and a microcode storage. A microinstruction of a microcode subroutine is stored in the microcode storage. The microinstruction has an indication of a microcode alias location. A microcode caller of the microcode subroutine is also stored in the microcode storage. The microcode caller is operable to specify a location of a parameter in the microcode alias location that is indicated by the microinstruction of the microcode subroutine. The apparatus also includes parameter location determination logic that is coupled with the microcode alias locations. The parameter location determination logic is operable, responsive to the microinstruction of the microcode subroutine, to receive the indication of the microcode alias location from the microinstruction and determine the location of the parameter specified in the microcode alias location indicated by the microinstruction.

US Patent:

20120079255, Mar 29, 2012

Filed:

Sep 25, 2010

Appl. No.:

12/890651

Inventors:

Jonathan D. Combs - Austin TX, US
Kulin N. Kothari - Austin TX, US

International Classification:

G06F 9/38

US Classification:

712239, 712E09045

Abstract:

Methods and apparatus to perform efficient indirect branch prediction operations are described. In one embodiment, a branch target buffer (BTB) stored a target address and a bimodal hysteresis counter for an indirect branch that has been encountered by a front-end of the processor during a time period. An indirect branch prediction logic then generates a prediction for an instruction corresponding to a indirect branch based on the stored bimodal hysteresis counter of the BTB. Other embodiments are also claimed and disclosed.

US Patent:

20120159129, Jun 21, 2012

Filed:

Dec 17, 2010

Appl. No.:

12/971819

Inventors:

Kameswar Subramaniam - Austin TX, US
Anthony Wojciechowski - Austin TX, US
Jonathan D. Combs - Austin TX, US

International Classification:

G06F 9/30

US Classification:

712210, 712E09029

Abstract:

A computer, circuit, and computer-readable medium are disclosed. In one embodiment, the processor includes an instruction decoder unit that can decode a macro instruction into at least one micro-operation with a set of data fields. The resulting micro-operation has at least one data field that is in a compressed form. The instruction decoder unit has storage that can store the micro-operation with the compressed-form data field. The instruction decoder unit also has extraction logic that is capable of extracting the compressed-form data field into an uncompressed-form data field. After extraction, the instruction decoder unit also can send the micro-operation with the extracted uncompressed-form data field to an execution unit. The computer also includes an execution unit capable of executing the sent micro-operation.