Jonathan Combs

US Patent:

8225046, Jul 17, 2012

Filed:

Sep 29, 2006

Appl. No.:

11/541174

Inventors:

Martin Licht - Round Rock TX, US
Jonathan Combs - Austin TX, US
Andrew Huang - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/00
G06F 13/00
G06F 13/28
G06F 1/26
G06F 1/32

US Classification:

711128, 713320

Abstract:

A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to track consecutive misses to ways of a cache, i. e. hits/reads to other ways of cache. Based on the usage of ways and the non-usage of other ways, the way predicting logic determines if a way is to be powered down. In response to determining a way is to be powered down, the way predicting logic generates a power signal to power down an associated. Furthermore, upon a subsequent hit to a powered down way, the way predicting logic toggles the power signal to power up the associated way to ensure performance.

US Patent:

20120284462, Nov 8, 2012

Filed:

Jul 17, 2012

Appl. No.:

13/551565

Inventors:

Martin Licht - Round Rock TX, US
Jonathan Combs - Austin TX, US
Andrew Huang - Austin TX, US

International Classification:

G06F 12/08

US Classification:

711128, 711E12018

Abstract:

A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.

US Patent:

20130219205, Aug 22, 2013

Filed:

Mar 15, 2013

Appl. No.:

13/843885

Inventors:

Martin Licht - Round Rock TX, US
Jonathan Combs - Austin TX, US
Andrew Huang - Austin TX, US

International Classification:

G06F 1/32

US Classification:

713324

Abstract:

A method and apparatus for disabling ways of a cache memory in response to history based usage patterns is herein described. Way predicting logic is to keep track of cache accesses to the ways and determine if an access to some ways are to be disabled to save power, based upon way power signals having a logical state representing a predicted miss to the way. One or more counters associated with the ways count accesses, wherein a power signal is set to the logical state representing a predicted miss when one of said one or more counters reaches a saturation value. Control logic adjusts said one or more counters associated with the ways according to the accesses.