Jonathan S Greene

US Patent:

6686353, Feb 3, 2004

Filed:

Jul 15, 1999

Appl. No.:

09/180994

Inventors:

Tatsuki Shiota - Kanagawa, JP
Shinsuke Yamagami - Tokyo, JP
Kenichiro Kataoka - Tokyo, JP
Noriaki Endo - Tokyo, JP
Hiroko Tanaka - Tokyo, JP
Doug Barnum - San Francisco CA
Jonathan Greene - Palo Alto CA
Wilna Moree - San Diego CA
Michele Ramirez Weinhouse - Escondido CA
Christine M. Tarby - Cardiff CA

Assignee:

Teijin Intellectual Property Center Limited - Osaka
Combichem, Inc. - CA

International Classification:

A61K 3155

US Classification:

514218, 51425213, 51425504, 51425301, 540575, 544359, 544398, 544403, 544360, 544379, 544396

Abstract:

Cyclic diamines of formula (I) or their pharmacologically acceptable acid addition salts, and their medical applications are described. These compounds inhibit the action of chemokines such as MIP-1a and/or MCP-1 on target cells, and are useful as a therapeutic drug and/or preventative drug in diseases, such as atherosclerosis, rheumatoid arthritis, and the like where blood monocytes and lymphocytes infiltrate into tissue.

US Patent:

7301821, Nov 27, 2007

Filed:

Oct 13, 2005

Appl. No.:

11/251074

Inventors:

Jonathan Greene - Palo Alto CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

G11C 16/04

US Classification:

36518528, 36518501, 36518508, 36518518

Abstract:

A method for storing data on nodes in memory cells of a non-volatile memory cell array including steps of setting non-volatile devices of the non-volatile memory cell array to a desired state, biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile memory cell array to an off state, loading data onto column lines of the non-volatile memory cell array and biasing non-volatile devices in a second set of rows in the memory cells of the non-volatile memory cell array to store data from the column lines on the nodes in the memory cells of the non-volatile memory cell array.

US Patent:

7430137, Sep 30, 2008

Filed:

Oct 8, 2007

Appl. No.:

11/868694

Inventors:

Jonathan W. Greene - Palo Alto CA, US
Fethi Dhaoui - Patterson CA, US
John McCollum - Saratoga CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

G11C 16/02
G11C 5/02
G11C 5/06
G06F 7/38
H03K 19/173
H03K 19/177
H03K 19/94

US Classification:

36518505, 365188, 36518902, 36523002, 326 38, 326 39, 326 44, 326 49

Abstract:

A non-volatile memory cell comprises a first floating gate transistor having a source, a drain, and a gate electrically coupled to a row line. A second floating gate transistor has a source, a drain, and a gate electrically coupled to the row line. A first p-channel MOS transistor has a source, a drain, and a gate, the drain of the first p-channel MOS transistor electrically coupled to the drain of the first floating gate transistor forming a first common node. A second p-channel MOS transistor has a source, a drain, and a gate, the first drain of the second p-channel MOS transistor electrically coupled to the drain of the second floating gate transistor forming a second common node, the gate of the second p-channel MOS transistor electrically coupled to the first common node, and the second common node electrically coupled to the gate of the first p-channel MOS transistor.

US Patent:

7463061, Dec 9, 2008

Filed:

Jul 19, 2005

Appl. No.:

11/185426

Inventors:

Jonathan W. Greene - Palo Alto CA, US
Vidya Bellippady - Cupertino CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H03K 19/20

US Classification:

326 41, 326113, 326 38

Abstract:

A reduced-leakage interconnect circuit includes a buffer having an input and an output, at least one multiplexer transistor coupled between a multiplexer input node and the input of the buffer, and a fixed-state multiplexer transistor coupled between a fixed-state multiplexer input node and the input of the buffer, the fixed-state multiplexer input node having a potential of either less than zero volts or more than Vpresent on it.

US Patent:

7573746, Aug 11, 2009

Filed:

Sep 26, 2007

Appl. No.:

11/861504

Inventors:

Jonathan Greene - Palo Alto CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

G11C 16/04

US Classification:

36518518, 36518505, 3651851, 36518526, 36518533, 36518525

Abstract:

A method for storing data on nodes in memory cells of a non-volatile memory cell array including steps of setting non-volatile devices of the non-volatile memory cell array to a desired state, biasing pull-up devices and non-volatile devices in a first set of rows of the non-volatile memory cell array to an off state, loading data onto column lines of the non-volatile memory cell array and biasing non-volatile devices in a second set of rows in the memory cells of the non-volatile memory cell array to store data from the column lines on the nodes in the memory cells of the non-volatile memory cell array.

US Patent:

7804321, Sep 28, 2010

Filed:

Sep 5, 2008

Appl. No.:

12/205656

Inventors:

Jonathan W. Greene - Palo Alto CA, US
John McCollum - Saratoga CA, US
Volker Hecht - Barsinghausen, DE

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H03K 19/00
H01L 25/00

US Classification:

326 16, 326 41, 326 47

Abstract:

An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.

US Patent:

7884640, Feb 8, 2011

Filed:

Dec 19, 2008

Appl. No.:

12/340358

Inventors:

Jonathan W Greene - Palo Alto CA, US
Gregory Bakker - San Jose CA, US
Vidyadhara Bellippady - San Jose CA, US
Volker Hecht - Barsinghausen, DE
Theodore Speers - San Jose CA, US

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H03K 19/173

US Classification:

326 38, 326 33, 326 41

Abstract:

A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.

US Patent:

7919977, Apr 5, 2011

Filed:

Aug 20, 2010

Appl. No.:

12/860004

Inventors:

Jonathan W. Greene - Palo Alto CA, US
John McCollum - Saratoga CA, US
Volker Hecht - Barsinghausen, DE

Assignee:

Actel Corporation - Mountain View CA

International Classification:

H03K 19/00
H01L 25/00

US Classification:

326 16, 326 41, 326 47

Abstract:

An FPGA architecture includes multiplexers having non-volatile switches having control gates coupled to word lines W, each word line associated with a row, the switches connecting to wiring tracks through buffers having a controllable ground connection NGND, at least some of the switches being a tie-off switch coupleable to one of a plurality of bitlines B, each bitline associated with column.