Jonathan C Hall

US Patent:

8447962, May 21, 2013

Filed:

Dec 22, 2009

Appl. No.:

12/644440

Inventors:

Christopher J. Hughes - Cupertino CA, US
Mayank Bomb - Hillsboro OR, US
Jason W. Brandt - Austin TX, US
Mark J. Buxton - Chandler AZ, US
Mark J. Charney - Lexington MA, US
Srinivas Chennupaty - Portland OR, US
Jesus Corbal - Barcelona, ES
Martin G. Dixon - Portland OR, US
Milind B. Girkar - Sunnyvale CA, US
Jonathan C. Hall - Hillsboro OR, US
Hideki (Saito) Ido - Sunnyvale CA, US
Peter Lachner - Heroldstatt, DE
Gilbert Neiger - Portland OR, US
Chris J. Newburn - South Beloit IL, US
Rajesh S. Parthasarathy - Hillsboro OR, US
Bret L. Toll - Hillsboro OR, US
Robert Valentine - Kiryat Tivon, IL
Jeffrey G. Wiedemeier - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00

US Classification:

712244

Abstract:

According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

US Patent:

20120144089, Jun 7, 2012

Filed:

Sep 30, 2011

Appl. No.:

13/250223

Inventors:

Jonathan C. Hall - Portland OR, US
Sailesh Kottapalli - San Jose CA, US
Andrew T. Forsyth - Kirkland WA, US

International Classification:

G06F 12/08

US Classification:

711 3, 711E12017

Abstract:

Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.

US Patent:

20120166761, Jun 28, 2012

Filed:

Dec 22, 2010

Appl. No.:

12/976616

Inventors:

Christopher J. Hughes - Santa Clara CA, US
Mark J. Charney - Lexington MA, US
Yen-Kuang Chen - Cupertino CA, US
Jesus Corbal - Barcelona, ES
Andrew T. Forsyth - Kirkland WA, US
Milind B. Girkar - Sunnyvale CA, US
Jonathan C. Hall - Hillsboro OR, US
Hideki Ido - Sunnyvale CA, US
Robert Valentine - Kiryat Tivon, IL
Jeffrey Wiedemeier - Austin TX, US

International Classification:

G06F 9/30

US Classification:

712 7, 712E09016

Abstract:

A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector.

US Patent:

20120254591, Oct 4, 2012

Filed:

Apr 1, 2011

Appl. No.:

13/078891

Inventors:

Christopher J. Hughes - Santa Clara CA, US
Jesus Corbal San Adrian - Barcelona, ES
Roger Espasa Sans - Mallorca, ES
Bret Toll - Hillsboro OR, US
Robert C. Valentine - Kiryat Tivon IL, US
Milind Baburao Girkar - Sunnyvale CA, US
Andrew Thomas Foryth - Kirkland WA, US
Edward Thomas Grochowski - San Jose CA, US
Jonathan Cannon Hall - Hillsboro OR, US

International Classification:

G06F 9/312

US Classification:

712205, 712E09033

Abstract:

Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask.

US Patent:

20130305020, Nov 14, 2013

Filed:

Sep 30, 2011

Appl. No.:

13/976707

Inventors:

Robert C. Valentine - Kiryat Tivon, IL
Jesus Corbal San Adrian - Barcelona, ES
Roger Espasa Sans - Barcelona, ES
Robert D. Cavin - San Francisco CA, US
Bret L. Toll - Hillsboro OR, US
Santiago Galan Duran - Molins De Rei, ES
Jeffrey G. Wiedemeier - Austin TX, US
Sridhar Samudrala - Austin TX, US
Milind Baburao Girkar - Sunnyvale CA, US
Edward Thomas Grochowski - San Jose CA, US
Jonathan Cannon Hall - Hillsboro OR, US
Dennis R. Bradford - Portland OR, US
James C. Abel - Phoenix AZ, US
Mark Charney - Lexington MA, US
Seth Abraham - Tempe AZ, US
Suleyman Sair - Chandler AZ, US
Andrew Thomas Forsyth - Kirkland WA, US
Lisa Wu - New York NY, US
Charles Yount - Phoenix AZ, US

International Classification:

G06F 9/30

US Classification:

712208, 712222

Abstract:

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

US Patent:

20210406026, Dec 30, 2021

Filed:

May 10, 2021

Appl. No.:

17/316680

Inventors:

- Santa Clara CA, US
Brian J. HICKMANN - Sherwood OR, US
Jonathan C. HALL - Hillsboro OR, US
Christopher J. HUGHES - Santa Clara CA, US

International Classification:

G06F 9/38
G06F 9/30
G06F 12/0875
G06F 12/1027
G06F 15/80
G06F 13/42

Abstract:

According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

US Patent:

20200394042, Dec 17, 2020

Filed:

Aug 27, 2020

Appl. No.:

17/004711

Inventors:

- Santa Clara CA, US
Jesus Corbal SAN ADRIAN - King City OR, US
Roger Espasa SANS - Barcelona, ES
Robert D. CAVIN - San Francisco CA, US
Bret L. TOLL - Hillsboro OR, US
Santiago Galan DURAN - Molins de Rei, ES
Jeffrey G. WIEDEMEIER - Austin TX, US
Sridhar SAMUDRALA - Austin TX, US
Milind Baburao GIRKAR - Sunnyvale CA, US
Edward Thomas GROCHOWSKI - San Jose CA, US
Jonathan Cannon HALL - Hillsboro OR, US
Dennis R. BRADFORD - Portland OR, US
James C. ABEL - Phoenix AZ, US
Mark CHARNEY - Lexington MA, US
Seth ABRAHAM - Tempe AZ, US
Suleyman SAIR - Phoenix AZ, US
Andrew Thomas FORSYTH - Kirkland WA, US
Lisa WU - New York NY, US
Charles YOUNT - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/30
G06F 9/34

Abstract:

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

US Patent:

20190250921, Aug 15, 2019

Filed:

Apr 29, 2019

Appl. No.:

16/398183

Inventors:

- Santa Clara CA, US
Brian J. HICKMANN - Sherwood OR, US
Jonathan C. HALL - Hillsboro OR, US
Christopher J. HUGHES - Santa Clara CA, US

International Classification:

G06F 9/38
G06F 9/30
G06F 12/1027
G06F 12/0875
G06F 13/42
G06F 15/80

Abstract:

According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.