Jonathan A Hall

US Patent:

20120144089, Jun 7, 2012

Filed:

Sep 30, 2011

Appl. No.:

13/250223

Inventors:

Jonathan C. Hall - Portland OR, US
Sailesh Kottapalli - San Jose CA, US
Andrew T. Forsyth - Kirkland WA, US

International Classification:

G06F 12/08

US Classification:

711 3, 711E12017

Abstract:

Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.

US Patent:

20210406026, Dec 30, 2021

Filed:

May 10, 2021

Appl. No.:

17/316680

Inventors:

- Santa Clara CA, US
Brian J. HICKMANN - Sherwood OR, US
Jonathan C. HALL - Hillsboro OR, US
Christopher J. HUGHES - Santa Clara CA, US

International Classification:

G06F 9/38
G06F 9/30
G06F 12/0875
G06F 12/1027
G06F 15/80
G06F 13/42

Abstract:

According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

US Patent:

20200394042, Dec 17, 2020

Filed:

Aug 27, 2020

Appl. No.:

17/004711

Inventors:

- Santa Clara CA, US
Jesus Corbal SAN ADRIAN - King City OR, US
Roger Espasa SANS - Barcelona, ES
Robert D. CAVIN - San Francisco CA, US
Bret L. TOLL - Hillsboro OR, US
Santiago Galan DURAN - Molins de Rei, ES
Jeffrey G. WIEDEMEIER - Austin TX, US
Sridhar SAMUDRALA - Austin TX, US
Milind Baburao GIRKAR - Sunnyvale CA, US
Edward Thomas GROCHOWSKI - San Jose CA, US
Jonathan Cannon HALL - Hillsboro OR, US
Dennis R. BRADFORD - Portland OR, US
James C. ABEL - Phoenix AZ, US
Mark CHARNEY - Lexington MA, US
Seth ABRAHAM - Tempe AZ, US
Suleyman SAIR - Phoenix AZ, US
Andrew Thomas FORSYTH - Kirkland WA, US
Lisa WU - New York NY, US
Charles YOUNT - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/30
G06F 9/34

Abstract:

A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.

US Patent:

20190250921, Aug 15, 2019

Filed:

Apr 29, 2019

Appl. No.:

16/398183

Inventors:

- Santa Clara CA, US
Brian J. HICKMANN - Sherwood OR, US
Jonathan C. HALL - Hillsboro OR, US
Christopher J. HUGHES - Santa Clara CA, US

International Classification:

G06F 9/38
G06F 9/30
G06F 12/1027
G06F 12/0875
G06F 13/42
G06F 15/80

Abstract:

According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

US Patent:

20180095895, Apr 5, 2018

Filed:

Sep 30, 2016

Appl. No.:

15/282841

Inventors:

- Santa Clara CA, US
Christopher B. Wilkerson - Portland OR, US
Roger Gramunt - Portland OR, US
Jonathan C. Hall - Hillsboro OR, US
Prabhat Jain - Hillsboro OR, US

International Classification:

G06F 12/121
G06F 12/0864

Abstract:

A processor includes a set associative cache and a cache controller. The cache controller makes an initial association between first and second groups of sampled sets in the cache and first and second cache replacement policies. Follower sets in the cache are initially associated with the more conservative of the two policies. Following cache line insertions in a first epoch, the associations between the groups of sampled sets and cache replacement policies are swapped for the next epoch. If the less conservative policy outperforms the more conservative policy during two consecutive epochs, the follower sets are associated with the less conservative policy for the next epoch. Subsequently, if the more conservative policy outperforms the less conservative policy during any epoch, the follower sets are again associated with the more conservative policy. Performance may be measured based the number of cache misses associated with each policy.

US Patent:

20170255470, Sep 7, 2017

Filed:

May 22, 2017

Appl. No.:

15/601003

Inventors:

- Santa Clara CA, US
Brian J. Hickmann - Sherwood OR, US
Jonathan C. Hall - Hillsboro OR, US
Christopher J. Hughes - Santa Clara CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/38
G06F 9/30

Abstract:

According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

US Patent:

20160378497, Dec 29, 2016

Filed:

Jun 26, 2015

Appl. No.:

14/752745

Inventors:

Roger Gramunt - Portland OR, US
Rammohan Padmanabhan - Beaverton OR, US
Gerardo A. Fernandez - Beaverton OR, US
David K. Li - Portland OR, US
Julio Gaga - Barcelona, ES
Michael Yang - Hillsboro OR, US
Jonathan C. Hall - Hillsboro OR, US

International Classification:

G06F 9/38
G06F 9/30

Abstract:

Embodiments of systems, methods, and apparatuses for thread selection and reservation station binding are disclosed. In an embodiment, an apparatus includes allocation hardware including reservation station binding logic to bind an operation to one of a plurality of reservation stations. In an embodiment, an apparatus includes thread selection logic to select a thread to be processed by a pipeline stage, wherein the thread selection logic to evaluate a plurality of conditions to select a thread, wherein the conditions include if a thread is active, if a thread has operations in an instruction queue, if a thread has available resources, and if a thread has no known stall.

US Patent:

20160179527, Jun 23, 2016

Filed:

Dec 23, 2014

Appl. No.:

14/581535

Inventors:

Jesus Corbal - Hillsboro OR, US
Dennis R. Bradford - Portland OR, US
Benjamin C. Chaffin - Portland OR, US
Taraneh Bahrami - San Jose CA, US
Jonathan C. Hall - Hillsboro OR, US
Thomas B. Maciukenas - Portland OR, US
Roger Gramunt - Portland OR, US
Rohan Sharma - Hillsboro OR, US

International Classification:

G06F 9/30

Abstract:

An apparatus and method for efficiently managing the architectural state of a processor. For example, one embodiment of a processor comprises: a source mask register to be logically subdivided into at least a first portion to store a usable portion of a mask value and a second portion to store an indication of whether the usable portion of the mask value has been updated; a control register to store an unusable portion of the mask value; architectural state management logic to read the indication to determine whether the mask value has been updated prior to performing a store operation, wherein if the mask value has been updated, then the architectural state management logic is to read the usable portion of the mask value from the first portion of the source mask register and zero out bits of the unusable portion of the mask value to generate a final mask value to be saved to memory, and wherein if the mask value has not been updated, then the architectural state management logic is to concatenate the usable portion of the mask value with the unusable portion of the mask value read from the control register to generate a final mask value to be saved to memory.