Jonathan T Holt

US Patent:

7396728, Jul 8, 2008

Filed:

Jun 29, 2005

Appl. No.:

11/170501

Inventors:

Ajith Varghese - McKinney TX, US
Narendra Singh Mehta - Dallas TX, US
Jonathan McAulay Holt - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/336
H01L 21/76

US Classification:

438296, 438424, 438427, 257E21546, 257E21549, 257E21573

Abstract:

A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body. A resist layer is formed on the hard mask layer that exposes and defines isolation regions. The hard mask layer is patterned and trench regions are formed using the hard mask layer as a mask. An oxide trench liner that induces compressive strain into active regions of the PMOS region is formed within trench regions of the PMOS region. A nitride trench liner that induces tensile strain into active regions of the NMOS region is formed within the NMOS trench regions.

US Patent:

20210117861, Apr 22, 2021

Filed:

Oct 16, 2020

Appl. No.:

17/072830

Inventors:

- Santa Clara CA, US
Qing Zhu - Rowlett TX, US
Jonathan Holt - Sachse TX, US
Tomonori Honda - Santa Clara CA, US

Assignee:

PDF Solutions, Inc. - Santa Clara CA

International Classification:

G06N 20/00
G06N 5/04
G06F 17/18
G06K 9/62

Abstract:

A sequence of models accumulates r-squared values for an increasing number of variables in order to quantify the importance of each variable to the prediction of a targeted yield or parametric response.

US Patent:

20210118754, Apr 22, 2021

Filed:

Oct 16, 2020

Appl. No.:

17/072817

Inventors:

- Santa Clara CA, US
Qing Zhu - Rowlett TX, US
Jonathan Holt - Sachse TX, US

Assignee:

PDF Solutions, Inc. - Santa Clara CA

International Classification:

H01L 21/66
G06N 20/00

Abstract:

A machine learning model for each die for imputing process control parameters at the die. The model is based on wafer sort parametric measurements at multiple test sites across the entire wafer, as well as yield results for the wafer. This allows for a better analysis of outlier spatial patterns leading to improved yield results.