Jonathan Stuart Jackson

US Patent:

20170293557, Oct 12, 2017

Filed:

Apr 11, 2016

Appl. No.:

15/095642

Inventors:

- Armonk NY, US
JONATHAN R. JACKSON - AUSTIN TX, US
MICHAEL S. SIEGEL - RALEIGH NC, US
WILLIAM J. STARKE - ROUND ROCK TX, US
JEFFREY A. STUECHELI - AUSTIN TX, US
DEREK E. WILLIAMS - AUSTIN TX, US

International Classification:

G06F 12/08

Abstract:

A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect coupled to the system memory and the multiple vertical cache hierarchies. A first cache memory in a first vertical cache hierarchy issues on the system interconnect a request for a target cache line. Responsive to the request and prior to receiving a systemwide coherence response for the request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the request. In response to the early indication of the systemwide coherence response and prior to receiving the systemwide coherence response, the first cache memory initiates processing to install the target cache line in the first cache memory.

US Patent:

20170293558, Oct 12, 2017

Filed:

Apr 11, 2016

Appl. No.:

15/095675

Inventors:

- ARMONK NY, US
JONATHAN R. JACKSON - AUSTIN TX, US
WILLIAM J. STARKE - ROUND ROCK TX, US
JEFFREY A. STUECHELI - AUSTIN TX, US
DEREK E. WILLIAMS - AUSTIN TX, US

International Classification:

G06F 12/08

Abstract:

A multiprocessor data processing system includes multiple vertical cache hierarchies supporting a plurality of processor cores, a system memory, and a system interconnect. In response to a load-and-reserve request from a first processor core, a first cache memory supporting the first processor core issues on the system interconnect a memory access request for a target cache line of the load-and-reserve request. Responsive to the memory access request and prior to receiving a systemwide coherence response for the memory access request, the first cache memory receives from a second cache memory in a second vertical cache hierarchy by cache-to-cache intervention the target cache line and an early indication of the systemwide coherence response for the memory access request. In response to the early indication and prior to receiving the systemwide coherence response, the first cache memory initiating processing to update the target cache line in the first cache memory.

US Patent:

20150178174, Jun 25, 2015

Filed:

Dec 24, 2013

Appl. No.:

14/140003

Inventors:

- Armonk NY, US
David W. Cummings - Round Rock TX, US
Jeff J. Frankeny - Austin TX, US
Jonathan R. Jackson - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/26

Abstract:

A method, system and computer-usable medium are disclosed for detecting the cause of a system hang in a verification environment. Hardware components associated with the design under test that are not included in the verification environment are replaced by software drivers. A dependency is set between a first driver and a second driver such that quiescing of the first driver is prevented until the second driver is quiesced. Each driver in a simulation test is designated to be either independent or dependent, with each dependent driver being associated with at least one independent driver. The independent driver is quiesced at a predetermined time. Dependent drivers do not quiesce until of their associated drivers have quiesced and completed all of their respectively issued instructions.

US Patent:

20150052311, Feb 19, 2015

Filed:

Sep 26, 2013

Appl. No.:

14/037923

Inventors:

- Armonk NY, US
Guy L. Guthrie - Austin TX, US
Jonathan R. Jackson - Austin TX, US
Derek E. Williams - Austin TX, US

International Classification:

G06F 9/46
G06F 12/08

US Classification:

711130

Abstract:

In a data processing system having a processor core and a shared memory system including a cache memory that supports the processor core, a transactional memory access request is issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing execution by the processor core. In response to receiving the transactional memory access request, dispatch logic of the cache memory evaluates the transactional memory access request for dispatch, where the evaluation includes determining whether the memory transaction has a failing transaction state. In response to determining the memory transaction has a failing transaction state, the dispatch logic refrains from dispatching the memory access request for service by the cache memory and refrains from updating at least replacement order information of the cache memory in response to the transactional memory access request.

US Patent:

20150052312, Feb 19, 2015

Filed:

Sep 26, 2013

Appl. No.:

14/038026

Inventors:

- Armonk NY, US
Guy L. Guthrie - Austin TX, US
Jonathan R. Jackson - Austin TX, US
Derek E. Williams - Austin TX, US

International Classification:

G06F 9/46
G06F 12/08

US Classification:

711130

Abstract:

A processing unit includes a processor core and a cache memory. Entries in the cache memory are grouped in multiple congruence classes. The cache memory includes tracking logic that tracks a transaction footprint including cache line(s) accessed by transactional memory access request(s) of a memory transaction. The cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class, forms a working set of ways in the congruence class containing cache line(s) within the transaction footprint and updates a replacement order of the cache lines in the congruence class. Based on membership of the at least one cache line in the working set, the update promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced.

US Patent:

20150052313, Feb 19, 2015

Filed:

Aug 15, 2013

Appl. No.:

13/967853

Inventors:

- Armonk NY, US
GUY L. GUTHRIE - Austin TX, US
JONATHAN R. JACKSON - Austin TX, US
DEREK E. WILLIAMS - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/12

US Classification:

711136

Abstract:

A processing unit includes a processor core and a cache memory. Entries in the cache memory are grouped in multiple congruence classes. The cache memory includes tracking logic that tracks a transaction footprint including cache line(s) accessed by transactional memory access request(s) of a memory transaction. The cache memory, responsive to receiving a memory access request that specifies a target cache line having a target address that maps to a congruence class, forms a working set of ways in the congruence class containing cache line(s) within the transaction footprint and updates a replacement order of the cache lines in the congruence class. Based on membership of the at least one cache line in the working set, the update promotes at least one cache line that is not the target cache line to a replacement order position in which the at least one cache line is less likely to be replaced.

US Patent:

20150052315, Feb 19, 2015

Filed:

Aug 15, 2013

Appl. No.:

13/967795

Inventors:

- ARMONK NY, US
GUY L. GUTHRIE - Austin TX, US
JONATHAN R. JACKSON - Austin TX, US
DEREK E. WILLIAMS - Austin TX, US

International Classification:

G06F 9/46
G06F 12/08

US Classification:

711145

Abstract:

In a data processing system having a processor core and a shared memory system including a cache memory that supports the processor core, a transactional memory access request is issued by the processor core in response to execution of a memory access instruction in a memory transaction undergoing execution by the processor core. In response to receiving the transactional memory access request, dispatch logic of the cache memory evaluates the transactional memory access request for dispatch, where the evaluation includes determining whether the memory transaction has a failing transaction state. In response to determining the memory transaction has a failing transaction state, the dispatch logic refrains from dispatching the memory access request for service by the cache memory and refrains from updating at least replacement order information of the cache memory in response to the transactional memory access request.

US Patent:

20140149622, May 29, 2014

Filed:

Nov 27, 2012

Appl. No.:

13/686095

Inventors:

- Armonk NY, US
Jonathan R. Jackson - Austin TX, US
Guy L. Guthrie - Austin TX, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 13/362

US Classification:

710244

Abstract:

In the verification of an integrated circuit design having arbitration logic which controls access from a plurality of requesters to a shared resource, an arbitration stall simulation mechanism selects one or more of the requesters for an extended stall procedure, and when a global counter expires, applies stalls having controlled durations to the selected requesters. The controlled durations can be randomly generated time periods within a preset range. The number of requesters subjected to the extended stall procedure can be randomly selected based on a predetermined percentage of requesters to stall. Local (requester-specific) code can perform the stalls for respective requesters using a stall duration inputs. The requester-specific codes can carry out the stalls using application program interface calls to override respective arbiter inputs from the requesters.