Jonathan I Lin

US Patent:

6813620, Nov 2, 2004

Filed:

Feb 27, 2002

Appl. No.:

10/083591

Inventors:

Jonathan Lin - Fremont CA
David Billings - Campbell CA
Mike Jorda - Fremont CA

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F 1730

US Classification:

707 10, 707 3, 707 8, 709216, 709217, 711148

Abstract:

A network device including a memory, a queue management unit, a memory management unit, and a search switching unit. The memory includes a plurality of memory banks. The queue management unit is configured to receive a plurality of search requests and to prioritize the search requests. The memory management unit is coupled to the queue management unit and the memory, and is configured to initiate a plurality of binary searches based on the plurality of search requests. Each binary search is executed simultaneously in different banks of the plurality of memory banks. The search switching unit is coupled to the memory and the memory management unit, and is configured to switch each binary search from one memory bank of to another memory bank after a predetermined number of search steps are performed by each binary search.

US Patent:

6920552, Jul 19, 2005

Filed:

Feb 27, 2002

Appl. No.:

10/083291

Inventors:

Jonathan Lin - Fremont CA, US
Yong Jiang - Fremont CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G03F007/38

US Classification:

713 1

Abstract:

A network device is provided which includes a device input, at least one port, a frequency doubler, a data I/O device, and a programmable delay locked loop. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal having double the frequency of the input signal. The data I/O device is configured to output data based upon a reference clock signal. The programmable delay locked loop is coupled to the device input and configured to receive an input signal and to automatically output an output signal being a predetermined amount out of phase from the input signal. An external clock signal received at the device input is input to the frequency doubler. The output of the frequency doubler is input to the data I/O device as a reference clock. Data (e. g. , from internal device logic) is output from the data I/O device to the at least one port.

US Patent:

6934866, Aug 23, 2005

Filed:

Mar 18, 2002

Appl. No.:

10/098337

Inventors:

Jonathan Lin - Fremont CA, US
Yong Jiang - Fremont CA, US

Assignee:

Broadcom Corporaton - Irvine CA

International Classification:

G06F001/12

US Classification:

713401

Abstract:

A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.

US Patent:

6965945, Nov 15, 2005

Filed:

Feb 27, 2002

Appl. No.:

10/083132

Inventors:

Jonathan Lin - Fremont CA, US
David Billings - Campbell CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F015/173

US Classification:

709242, 707 3, 37039531

Abstract:

A network device including at least one network port, a clock, address resolution (ARL) tables, and address resolution logic. The at least one network port is configured to send and receive a data packet. The clock is for generating a timing signal. The ARL tables are configured to store and maintain data related to port addresses of the network device. The address resolution logic is coupled to the ARL tables and configured to perform a search and an update to data into the ARL tables based on the data packet, to calculate a current range of the search, to determine an intended result of the update, and to block the update when the intended result will move data out of the current range of the search, the search and the update being performed concurrently during alternating slots of the timing signal.

US Patent:

6981058, Dec 27, 2005

Filed:

Feb 27, 2002

Appl. No.:

10/083594

Inventors:

Jonathan Lin - Fremont CA, US
David Billings - Campbell CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G06F015/173

US Classification:

709242, 707 3, 37039531

Abstract:

A network device including at least one network port, a clock, address resolution logic (ARL) tables, and address resolution logic. The clock generates a timing signal. The ARL tables are configured to store and maintain data related to port addresses of the network device. The address resolution logic is coupled to the ARL tables and the clock, and configured to search the ARL tables and to perform learning concurrently during alternating slots of the timing signal. Upon receiving a data packet at the at least one port, the address resolution logic is configured to search the ARL tables for a destination address based on the data packet. When the destination address is found, the address resolution logic is configured to update a related record of the ARL tables based on the learning, the address resolution logic configured to perform searches and updates.

US Patent:

7010535, Mar 7, 2006

Filed:

Oct 18, 2004

Appl. No.:

10/965728

Inventors:

Jonathan Lin - Fremont CA, US
David Billings - Campbell CA, US
Mike Jorda - Fremont CA, US

Assignee:

Broadcom Corportion - Irvine CA

International Classification:

G06F 17/30

US Classification:

707 10, 707 3, 707 8, 709216, 709217, 711148

Abstract:

A network device including a memory, a queue management unit, a memory management unit, and a search switching unit. The memory includes a plurality of memory banks. The queue management unit is configured to receive a plurality of search requests and to prioritize the search requests. The memory management unit is coupled to the queue management unit and the memory, and is configured to initiate a plurality of binary searches based on the plurality of search requests. Each binary search is executed simultaneously in different banks of the plurality of memory banks. The search switching unit is coupled to the memory and the memory management unit, and is configured to switch each binary search from one memory bank of to another memory bank after a predetermined number of search steps are performed by each binary search.

US Patent:

7024576, Apr 4, 2006

Filed:

Jul 14, 2005

Appl. No.:

11/180628

Inventors:

Jonathan Lin - Fremont CA, US
Yong Jiang - Fremont CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

G04F 8/00

US Classification:

713400

Abstract:

A network device includes an input, at least one port, a frequency doubler, a data I/O device, and a variable delay circuit. The input is for receiving an external clock signal. The frequency doubler is coupled to the input and configured to receive an input signal and output an output signal with a frequency double that of the input signal. The data I/O device is configured to output data to the at least one port based on a reference clock signal. The variable delay circuit is located between the data I/O device and at least one port. An external clock signal received at the input is input into the frequency doubler. The output signal of the frequency doubler is applied to the data I/O device as the reference clock signal, and the output data is delayed by the variable delay circuit.

US Patent:

7068652, Jun 27, 2006

Filed:

Mar 6, 2002

Appl. No.:

10/090797

Inventors:

Jonathan Lin - Fremont CA, US
Somayajulu Pullela - San Jose CA, US
David Billings - Campbell CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04J 1/16

US Classification:

370389

Abstract:

A network device includes at least one network port, a masks table, a rules table, a pointers table, and a fast filter processor. The masks table contains filter information and a mask key. The rules table contains corresponding rules to the filter information and is related to the mask table by the mask key. The pointers table contains boundary data related to the rules for corresponding filter information. The fast filter processor is coupled to the mask table, the rules table and the pointers table, and configured to perform at least one binary search for at least one rule related to a data packet received by the network device at the at least one network port, the binary search being limited based on the boundary data in the pointers table.