Jonathan D Reid

US Patent:

6458262, Oct 1, 2002

Filed:

Mar 9, 2001

Appl. No.:

09/802490

Inventors:

Jonathan David Reid - Sherwood OR

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

C25D 2114

US Classification:

205 82, 2042286, 2042292, 204232, 204237, 205101

Abstract:

The present invention provides methods and apparatus for analysis and monitoring of electrolyte bath composition. Based on analysis results, the invention controls electrolyte bath composition and plating hardware. Thus, the invention provides control of electroplating processes based on plating bath composition data. The invention accomplishes this by incorporating accurate bath component analysis data into a feedback control mechanism for electroplating. Bath electrolyte is treated and analyzed in a flow-through system in order to identify plating bath component concentrations and based on the results, the plating bath formulation and plating process are controlled.

US Patent:

6471845, Oct 29, 2002

Filed:

Dec 15, 1999

Appl. No.:

09/461849

Inventors:

John O. Dukovic - Pleasantville NY
Erick G. Walton - Underhill VT
Peter S. Locke - Hopewell Junction NY
Panayotis C. Andricacos - Croton-on-Hudson NY
James E. Fluegel - Rhinebeck NY
Evan Patton - Portland OR
Jonathan Reid - Sherwood OR

Assignee:

International Business Machines Corporation - Armonk NY
Novellus Systems, Inc. - San Jose CA

International Classification:

C25D 2112

US Classification:

205 81, 205101, 137 93

Abstract:

A method for controlling the composition of a chemical bath in which predictive dosing is used to account for changes in the composition of the bath in which the operating characteristics of the process are partitioned into a plurality of operating modes and the consumption or generation of materials related to the process are determined empirically and additions of material are made as appropriate.

US Patent:

6527920, Mar 4, 2003

Filed:

Nov 3, 2000

Appl. No.:

09/706272

Inventors:

Steven T. Mayer - Lake Oswego OR
Evan E. Patton - Portland OR
Robert L. Jackson - San Jose CA
Jonathan D. Reid - Sherwood OR

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

C25B 1500

US Classification:

204237, 204252, 204263, 204264, 204295, 204296, 204266

Abstract:

An electroplating apparatus prevents anode-mediated degradation of electrolyte additives by creating a mechanism for maintaining separate anolyte and catholyte and preventing mixing thereof within a plating chamber. The separation is accomplished by interposing a porous chemical transport barrier between the anode and cathode. The transport barrier limits the chemical transport (via diffusion and/or convection) of all species but allows migration of ionic species (and hence passage of current) during application of sufficiently large electric fields within electrolyte.

US Patent:

6551483, Apr 22, 2003

Filed:

May 10, 2001

Appl. No.:

09/853959

Inventors:

Steven T. Mayer - Clackamas OR
Jonathan Reid - Sherwood OR
Robert Contolini - Clackamas OR

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

C25D 2112

US Classification:

205 81, 205 87, 205102, 205103, 205104

Abstract:

Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.

US Patent:

6551487, Apr 22, 2003

Filed:

May 31, 2001

Appl. No.:

09/872341

Inventors:

Jonathan D. Reid - Sherwood OR
Steven T. Mayer - Lake Oswego OR
Seshasayee Varadarajan - Wilsonville OR
David C. Smith - Lake Oswego OR
Evan E. Patton - Portland OR
Dinesh S. Kalakkad - Portland OR
Gary Lind - Penn Valley CA

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

C25D 500

US Classification:

205137, 205143, 205149

Abstract:

The orientation of a wafer with respect to the surface of an electrolyte is controlled during an electroplating process. The wafer is delivered to an electrolyte bath along a trajectory normal to the surface of the electrolyte. Along this trajectory, the wafer is angled before entry into the electrolyte for angled immersion. A wafer can be plated in an angled orientation or not, depending on what is optimal for a given situation. Also, in some designs, the wafers orientation can be adjusted actively during immersion or during electroplating, providing flexibility in various electroplating scenarios.

US Patent:

6554914, Apr 29, 2003

Filed:

Feb 2, 2001

Appl. No.:

09/776704

Inventors:

Robert T. Rozbicki - San Jose CA
Ronald Allan Powell - San Carlos CA
Erich Klawuhn - San Jose CA
Michal Danek - Sunnyvale CA
Karl B. Levy - Los Altos CA
Jonathan David Reid - Sherwood OR
Mukul Khosla - San Jose CA
Eliot K. Broadbent - Beaverton OR

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

C23C 824

US Classification:

148238, 148282

Abstract:

The present invention pertains to systems and methods for passivating the copper seed layer deposited in Damascene integrated circuit manufacturing. More specifically, the invention pertains to systems and methods for depositing the copper seed layer by physical vapor deposition, while passivating the copper during or immediately after the deposition in order to prevent excessive oxidation of the copper. The invention is applicable to dual Damascene processing.

US Patent:

6562204, May 13, 2003

Filed:

May 10, 2001

Appl. No.:

09/854230

Inventors:

Steven T. Mayer - Lake Oswego OR
Jonathan Reid - Sherwood OR
Robert Contolini - Lake Oswego OR

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

B23H 302

US Classification:

2042299, 2042298, 2042307, 2042971, 20429714

Abstract:

Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.

US Patent:

6569299, May 27, 2003

Filed:

May 18, 2000

Appl. No.:

09/574666

Inventors:

Jonathan David Reid - Sherwood OR
Robert J. Contolini - Lake Oswego OR
John Owen Dukovic - Plesantville NY

Assignee:

Novellus Systems, Inc. - San Jose CA
International Business Machines, Corp. - Armonk NY

International Classification:

C25B 1300

US Classification:

204282, 204283, 20429711, 204238, 204259, 205148, 205 68

Abstract:

An anode includes an anode cup, a membrane and ion source material, the anode cup and membrane forming an enclosure in which the ion source material is located. The anode cup includes a base section having a central aperture and the membrane also has a central aperture. A jet is passed through the central apertures of the base section of the anode cup and through the membrane allowing plating solution to be directed at the center of a wafer being electroplated.