Joseph Living Biran

age ~78

from Sunnyvale, CA

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Also known as:

Joseph B Biran
Biran Joseph

Phone and address:: 1466 Dartshire Ct, Sunnyvale, CA 94087

Connected to:

Joseph Biran Phones & Addresses

1466 Dartshire Ct, Sunnyvale, CA 94087
746 Devonshire Way, Sunnyvale, CA 94087
Campbell, CA
361 Vaughn Ave, San Jose, CA 95128 • 4088575071
Santa Clara, CA
361 Vaughn Ave, San Jose, CA 95128

Skills

Team Building • Development Projects • Planning • Specifications • Signal Integrity • Infrastructure • Signal Design • Analog • Bandgap References • San • Technical Marketing • Wan • Spi • Film • Lithography • Design • Thin • Code Coverage • Marketing Support • Analyzer • Ic • Leadership • Rfq • Signal • Comparators • Fma • Product Planning • Networking • Cell • Ip • Engineers • Engineering • Circuits • Mixed Signal • Dsp • Supply • Motor Control • R&D • Power Systems • Gui • Rx • Amplifiers • Bicmos • Controllers • High Voltage • Business Acumen • Sfi • Asic • Business Development • Amps • Test Systems • Modeling • Lan • Pll • Strategic Planning • Characterization • Marketing • Serdes • Data Acquisition • Dc Circuits • Test Development • Mass Production • Power Supplies • System Development • Interfaces • Electronics • Power Management • Medical Devices • Pmi • Cmos • Program Management • Microelectronics • Digital Libraries • Design Tools • Military • Optimization • Voltage • Infiniband • Oif

Resumes

Joseph Biran

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Location:

Sunnyvale, CA

Skills:

Team Building
Development Projects
Planning
Specifications
Signal Integrity
Infrastructure
Signal Design
Analog
Bandgap References
San
Technical Marketing
Wan
Spi
Film
Lithography
Design
Thin
Code Coverage
Marketing Support
Analyzer
Ic
Leadership
Rfq
Signal
Comparators
Fma
Product Planning
Networking
Cell
Ip
Engineers
Engineering
Circuits
Mixed Signal
Dsp
Supply
Motor Control
R&D
Power Systems
Gui
Rx
Amplifiers
Bicmos
Controllers
High Voltage
Business Acumen
Sfi
Asic
Business Development
Amps
Test Systems
Modeling
Lan
Pll
Strategic Planning
Characterization
Marketing
Serdes
Data Acquisition
Dc Circuits
Test Development
Mass Production
Power Supplies
System Development
Interfaces
Electronics
Power Management
Medical Devices
Pmi
Cmos
Program Management
Microelectronics
Digital Libraries
Design Tools
Military
Optimization
Voltage
Infiniband
Oif

Us Patents

Electrostatic Discharge (Esd) Protection Circuit With Reduced Node Capacitance
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US Patent:

59738979, Oct 26, 1999
Filed:

Jul 9, 1997
Appl. No.:

8/890106
Inventors:

Ion E. Opris - Sunnyvale CA
Joseph Biran - Sunnyvale CA
Assignee:

National Semiconductor Corporation - Santa Clara CA
International Classification:

H02H 900
US Classification:

361 56
Abstract:

An electrostatic discharge (ESD) protection circuit with reduced high frequency signal distortion includes an additional input shunting diode and a voltage follower amplifier. This second diode and the original input shunting diode are connected in series between the circuit node to be protected and circuit ground so as to limit the voltage level at such node during an ESD event. The voltage follower amplifier maintains a substantially constant voltage across this second diode, thereby maintaining a substantially constant diode junction capacitance. Hence, with the introduction of this additional, serially connected junction capacitance of the second diode, the nonlinear input capacitance responsible for input signal distortion is reduced, plus with a substantially constant diode junction capacitance due to the use of the voltage follower amplifier, such reduced capacitance remains substantially more constant over variations in the input signal voltage.

Method For Coating The Edge Of A Printed Circuit Board To Improve Its Moisture Resistance
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US Patent:

42787076, Jul 14, 1981
Filed:

May 19, 1980
Appl. No.:

6/151010
Inventors:

Joseph Biran - Sunnyvale CA
Assignee:

Hewlett-Packard Company - Palo Alto CA
International Classification:

H05K 328
US Classification:

427 96
Abstract:

By sealing the periphery of a printed circuit board, the previously exposed edges of the board are substantially prevented from moisture wicking. This sealing of the periphery can be made concurrently with the plating of through-holes on the board. With this process, current leakage paths due to board moisture wicking within the board is significantly reduced.

Compensation Of V.sub.be Non-Linearities Over Temperature By Using High Base Sheet Resistivity Devices
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US Patent:

42426936, Dec 30, 1980
Filed:

Dec 26, 1978
Appl. No.:

5/972742
Inventors:

Joseph Biran - Sunnyvale CA
Assignee:

Fairchild Camera & Instrument Corporation - Mountain View CA
International Classification:

H01L 2356
US Classification:

357 28
Abstract:

In a transistor circuit a linear relationship between V. sub. BE and temperature is obtained by using high base sheet resistivity devices, such as super beta NPN transistors, or lateral PNP transistors. Alternatively, high base sheet resistivity devices are fabricated having a non-linear V. sub. BE vs. temperature relationship that is matched to the non-linear V. sub. BE vs. temperature relationship of NPN devices and/or the non-linear resistivity of diffused resistors over temperature, such that the sum or difference of the non-linear terms will exactly cancel, providing a linear voltage vs. temperature relationship for the circuit as a whole.