Joseph A Castro

Address:

8328 Vly Strm Ave, Las Vegas, NV 89131

Phone:

7028390983

VIN:

WBAWB33557PV74315

Make:

BMW

Model:

3 SERIES

Year:

2007

US Patent:

7405158, Jul 29, 2008

Filed:

Jan 19, 2005

Appl. No.:

11/038592

Inventors:

Ken Kaung Lai - Milpitas CA, US
Ravi Rajagopalan - Sunnyvale CA, US
Amit Khandelwal - Santa Clara CA, US
Madhu Moorthy - Santa Clara CA, US
Srinivas Gandikota - Santa Clara CA, US
Joseph Castro - Fremont CA, US
Cheryl Knepfler - Fremont CA, US
Ping Jian - San Jose CA, US
Hongbin Fang - Mountain View CA, US
Chao-Ming Huang - Hsin Chu, TW
Ming Xi - Palo Alto CA, US
Michael X. Yang - Palo Alto CA, US
Hua Chung - San Jose CA, US
Jeong Soo Byun - Cupertino CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/44

US Classification:

438680, 438677, 257E21171, 257E21585

Abstract:

In one embodiment of the invention, a method for forming a tungsten-containing layer on a substrate is provided which includes positioning a substrate containing a barrier layer disposed thereon in a process chamber, exposing the substrate to a first soak process for a first time period and depositing a nucleation layer on the barrier layer by flowing a tungsten-containing precursor and a reductant into the process chamber. The method further includes exposing the nucleation layer to a second soak process for a second time period and depositing a bulk layer on the nucleation layer. In one example, the barrier layer contains titanium nitride, the first and second soak processes independently comprise at least one reducing gas selected from the group consisting of hydrogen, silane, disilane, dichlorosilane, borane, diborane, derivatives thereof and combinations thereof and the nucleation layer may be deposited by an atomic layer deposition process or a pulsed chemical vapor deposition process while the bulk layer may be deposited by a chemical vapor deposition process or a physical vapor deposition process.

US Patent:

7745333, Jun 29, 2010

Filed:

Jul 24, 2008

Appl. No.:

12/179002

Inventors:

Ken Kaung Lai - Milpitas CA, US
Ravi Rajagopalan - Sunnyvale CA, US
Amit Khandelwal - Santa Clara CA, US
Madhu Moorthy - Santa Clara CA, US
Srinivas Gandikota - Santa Clara CA, US
Joseph Castro - Fremont CA, US
Avgerinos V. Gelatos - Redwood City CA, US
Cheryl Knepfler - Fremont CA, US
Ping Jian - San Jose CA, US
Hongbin Fang - Mountain View CA, US
Chao-Ming Huang - Hsin Chu, TW
Ming Xi - Palo Alto CA, US
Michael X. Yang - Palo Alto CA, US
Hua Chung - San Jose CA, US
Jeong Soo Byun - Cupertino CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/44

US Classification:

438680, 257E2117, 257E21171, 257E21585

Abstract:

In one embodiment of the invention, a method for forming a tungsten-containing layer on a substrate is provided which includes positioning a substrate containing a barrier layer disposed thereon in a process chamber, exposing the substrate to a first soak process for a first time period and depositing a nucleation layer on the barrier layer by flowing a tungsten-containing precursor and a reductant into the process chamber. The method further includes exposing the nucleation layer to a second soak process for a second time period and depositing a bulk layer on the nucleation layer. In one example, the barrier layer contains titanium nitride, the first and second soak processes independently comprise at least one reducing gas selected from the group consisting of hydrogen, silane, disilane, dichlorosilane, borane, diborane, derivatives thereof and combinations thereof and the nucleation layer may be deposited by an atomic layer deposition process or a pulsed chemical vapor deposition process while the bulk layer may be deposited by a chemical vapor deposition process or a physical vapor deposition process.

US Patent:

20110093132, Apr 21, 2011

Filed:

Oct 19, 2009

Appl. No.:

12/581702

Inventors:

Cheng P. Tan - Fremont CA, US
Keith A. Cox - Campbell CA, US
Robert B. Sexton - Sunnyvale CA, US
Joseph J. Castro - San Jose CA, US
Bryan R. Hoover - San Jose CA, US

Assignee:

APPLE INC. - Cupertino CA

International Classification:

G05D 23/19

US Classification:

700299

Abstract:

Some embodiments provide a system that manages the temperature of a component in an electronic device. During operation, the system receives, from the component, a temperature offset of the component and a thermal state boundary associated with the temperature offset. Next, the system uses the temperature offset and the thermal state boundary to control the temperature of the component.

US Patent:

20210117265, Apr 22, 2021

Filed:

Dec 7, 2020

Appl. No.:

17/114388

Inventors:

- Cupertino CA, US
Joshua H. Berlin - San Francisco CA, US
Joseph J. Castro - San Jose CA, US
Hardik K. Doshi - Los Altos CA, US
Joel N. Kerr - San Jose CA, US
Kerry J. Kopp - Los Altos Hills CA, US
Michael J. Smith - San Jose CA, US

International Classification:

G06F 11/07
G06F 11/30

Abstract:

One embodiment provides for a data processing system comprising multiple independent processors to execute multiple operating system environments of the data processing system, the multiple operating system environments to enable operation of multiple regions of a computing device associated with the data processing system. The multiple operating system environments are interconnected via a transport agnostic communication link. In response to detection of a fatal error in one or more of the multiple operating system environments, the multiple operating system environments coordinate performance of multiple separate error handling operations within the multiple operating system environments to generate a combined error log. The combined error log includes operational states of the multiple operating system environments.

US Patent:

20190179695, Jun 13, 2019

Filed:

Sep 28, 2018

Appl. No.:

16/147330

Inventors:

- Cupertino CA, US
Joshua H. Berlin - San Francisco CA, US
Joseph J. Castro - San Jose CA, US
Hardik K. Doshi - Los Altos CA, US
Joel N. Kerr - San Jose CA, US
Kerry J. Kopp - Los Altos Hills CA, US
Michael J. Smith - San Jose CA, US

International Classification:

G06F 11/07

Abstract:

One embodiment provides for a data processing system comprising multiple independent processors to execute multiple operating system environments of the data processing system, the multiple operating system environments to enable operation of multiple regions of a computing device associated with the data processing system. The multiple operating system environments are interconnected via a transport agnostic communication link. In response to detection of a fatal error in one or more of the multiple operating system environments, the multiple operating system environments coordinate performance of multiple separate error handling operations within the multiple operating system environments to generate a combined error log. The combined error log includes operational states of the multiple operating system environments.

US Patent:

20180348850, Dec 6, 2018

Filed:

Sep 29, 2017

Appl. No.:

15/720916

Inventors:

- Cupertino CA, US
Gopal Thirumalai Narayanan - Santa Clara CA, US
Siddharth P. Shah - San Jose CA, US
Joseph J. Castro - San Jose CA, US
Craig S. Forbell - Los Gatos CA, US
Christopher M. Aycock - San Francisco CA, US
Varaprasad V. Lingutla - Fremont CA, US

International Classification:

G06F 1/32
G06F 9/44
G06F 13/42

Abstract:

A method from managing power state transitions in a computing system is disclosed. A processor may initiate a change in power state from a first initial power state to a first new power state and, in response to initiating the change, send an initial notification to a system integrated circuit using a first communication channel, and deactivate the first communication based on responses to the initial notification. The processor may enter the first new power state in response to the deactivation of the first communication channel, and send a final notification to a management controller using a second communication channel. The management controller may send a message to the system integrated circuit upon receiving the final notification. The system integrated circuit may then transition from a second initial power state to a second new power state based on the message.