Joseph J Chan

US Patent:

6351020, Feb 26, 2002

Filed:

Nov 12, 1999

Appl. No.:

09/438618

Inventors:

Marc L. Tarabbia - Austin TX
Joseph Y. Chan - Austin TX
Geoffrey B. Hall - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H01L 2900

US Classification:

257532, 275307, 275595

Abstract:

A cumulative capacitor structure with desirably constant capacitance characteristics is disclosed. In one embodiment, the cumulative capacitor includes a set of four capacitors coupled in parallel between first and second terminals of the cumulative capacitor. In one embodiment, the first capacitor is comprised of a top plate formed of an n-type polysilicon coupled to the first terminal, a bottom plate comprised of a first accumulation/depletion region such as an n-well region coupled to the second terminal, and a first dielectric region between its top and bottom plates. The second capacitor has an n-type polysilicon terminal top plate coupled to the second terminal, an accumulation/depletion region bottom plate coupled to the first terminal, and a dielectric between its top and bottom plate. A third capacitor has a p-type polysilicon top plate coupled to the first terminal, an accumulation/depletion region bottom plate coupled to the second terminal, and a third dielectric region between its top and bottom plates. The fourth capacitor has a p-type polysilicon terminal coupled to the second terminal, an accumulation/depletion region bottom plate coupled to the first terminal, and a dielectric between its top and bottom plates.

US Patent:

6707339, Mar 16, 2004

Filed:

Nov 22, 2002

Appl. No.:

10/301992

Inventors:

Kiyoshi Kase - Austin TX
Joseph Y. Chan - Gurnee IL
Chunhe Zhao - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03F 345

US Classification:

330255, 330260, 330261

Abstract:

An operational amplifier circuit ( ) uses a first operational amplifier ( ) to selectively provide a boosted drive current in response to an input signal voltage transitioning. The boosted driver current is used by a second operational amplifier ( ) having a single high gain stage ( ). The output drive current of the operational amplifier circuit ( ) is increased to a predetermined maximum value for a predetermined time after an input signal transition in order to source increased current to a capacitive or inductive load only during output signal transitions. Separate current boost circuits ( ) in each of the first and second operational amplifiers enable early signal transition detection and ensure continuation of increased current until completion of the signal transition.

US Patent:

63271265, Dec 4, 2001

Filed:

Jan 28, 2000

Appl. No.:

9/494055

Inventors:

James W. Miller - Austin TX
Michael G. Khazhinsky - Austin TX
Geoffrey B. Hall - Austin TX
Jose A. Camarena - Austin TX
Joseph Chan - Round Rock TX
Fujio Takeda - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H02H 900

US Classification:

361 56

Abstract:

A circuit (600) provides Electrostatic Discharge (ESD) protection for internal elements in an integrated circuit during an ESD event. The circuit (600) includes cascoded NMOSFETs (614, 616), with the upper NMOSFET (614) connected to voltage divider circuitry (628). The voltage divider circuitry (628) provides a first bias voltage to the gate of the upper NMOSFET (614) during an ESD event and a second bias voltage during normal operation. Preferably, the first bias voltage is approximately 1/2 of the drain voltage of the upper NMOSFET (614). Under these bias conditions the cascoded NMOSFETs exhibit a maximum voltage threshold for initiation of parasitic lateral bipolar conduction.

US Patent:

55460470, Aug 13, 1996

Filed:

Feb 27, 1995

Appl. No.:

8/395126

Inventors:

Joseph Y. Chan - Austin TX
Mathew A. Rybicki - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03F 345

US Classification:

330253

Abstract:

An operational amplifier (10) having an inverted output (20) ranging from a return voltage up to a rail supply voltage includes an amplifying stage (12) and: a linear output inverter (14). The linear output inverter (14) includes an inverting pull down stage (16), an output stage controller (17), and a pull up output stage (18). The inverting pull down stage (16) operates to pull the inverted output down to the return voltage when the inverted output is below a first threshold. The pull up output stage (18) operates to pull the inverted output up to the rail voltage when the inverted output (20) is above a second threshold. The first threshold is greater than the second threshold such that both the inverting pull down stage (16) and the pull up output stage (18) operate when the inverted output (20) lies between the first threshold and the second threshold.

US Patent:

61374296, Oct 24, 2000

Filed:

Mar 8, 1999

Appl. No.:

9/265238

Inventors:

Joseph Y. Chan - Austin TX
David Yatim - Austin TX
Kiyoshi Kase - Pflugerville TX
Paul Astrachan - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03M 300

US Classification:

341143

Abstract:

A data converter (10) and a method for attenuating noise in an output signal generated by the data converter (10). The data converter (10) includes a sigma-delta modulator (16), a digital-to-analog converter (17), a clock generator (19) connected to the digital-to-analog converter (17), and a clock control circuit (18) connected to the clock generator (19). The clock control circuit (18) enables or disables the clock generator (19) in accordance with the single-bit digital signal to cause a notch characteristic in the output signal for attenuating noise in the output signal.

US Patent:

58776540, Mar 2, 1999

Filed:

Dec 2, 1996

Appl. No.:

8/758658

Inventors:

Joseph Yves Chan Yan Fong - Austin TX
Mathew A. Rybicki - Austin TX

Assignee:

Motorola Inc. - Austin TX

International Classification:

H03F 114

US Classification:

330292

Abstract:

A class A driver circuit (30) has an output stage with a plurality of selectable current sources (42). The selectable current sources (42) are used to optimize the drive capability of the output stage of the class A driver circuit (30) for different applications having different output impedance. In one embodiment, the selectable current sources (42) may be selectable, or switchable, using software programmed by a user. In another embodiment, the current sources may be automatically selected, based on sensing the output current provided to a resistive load. Also, in yet another embodiment, the selectable current sources (42) may be selectable based on the input signal of a first stage amplifier (32). A Miller compensation network (40) includes digitally controlled, switchable capacitors (129) and resistors (128), and provides the necessary amount of Miller compensation for the selected current sources.