Joseph Garcia

US Patent:

8274306, Sep 25, 2012

Filed:

Mar 31, 2011

Appl. No.:

13/066229

Inventors:

Joseph P. Garcia - La Plata MD, US

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H03K 19/00

US Classification:

326 8, 326 47

Abstract:

A physically unclonable function (PUF) device, with corresponding method, is provided for characterizing an integrated circuit. The PUF device includes a digital clock manager (DCM), a Butterfly circuit incorporated within the integrated circuit, and a shift register. The DCM receives a clock input signal (CLK) and imposes a temporal offset to produce a phase-shift signal (PS). The Butterfly circuit receives a first excite signal as said CLK and a second excite signal as said PS. In response, the Butterfly circuit produces an output that shifts state in response to a non-concurrent change in the CLK and PS. The shift register increments a shift count in response to the output.

US Patent:

20050237229, Oct 27, 2005

Filed:

Apr 21, 2004

Appl. No.:

10/829066

Inventors:

Frank Gong - Syosset NY, US
Curt Croley - Stony Brook NY, US
Joseph Garcia - Levittown NY, US

International Classification:

H03M011/00

US Classification:

341023000

Abstract:

Systems and methodologies are provided for fabrication of a self contained key pad module having a top cover and a bottom cover. The top cover and the bottom cover encapsulate and/or sandwich a stack of keypad components via an over mold procedure that is performed around the stack. The packed stack between the top cover and the bottom cover can include a flex member, an electro luminous panel, and a silicone membrane with a plurality of keys thereupon.

US Patent:

59908297, Nov 23, 1999

Filed:

Jul 3, 1998

Appl. No.:

9/131844

Inventors:

Joseph P. Garcia - Waldorf MD

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H01Q 322

US Classification:

342368

Abstract:

A computer vision system is disclosed that utilizes a spinning array of podetectors. The array is rotated about the focal plane of a lens and scans all the possible orientations and positions of the edges of the unknown object. In one embodiment, the photodetectors are elongated so as to provide for maximum light gathering ability along the direction of elongation and a minimum light gathering ability in the direction perpendicular to the direction of elongation. In other embodiments, optical means are used to focus the image onto conventional photodetectors while still having the ability to more efficiently determine edge segments of unknown objects. The system efficiently and rapidly implements the wavelet projection transform to characterize-multi-scale edge segment features of an image of an unknown object. An imaging radar system that utilizes a spinning antenna system having frequency scanning provisions is also disclosed.

US Patent:

59095202, Jun 1, 1999

Filed:

Aug 25, 1997

Appl. No.:

8/934012

Inventors:

Joseph P. Garcia - Waldorf MD

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

G06H 936

US Classification:

382303

Abstract:

A noise coding processor employing pipeline processing techniques is disclosed. The noise coding processor employs parallel pseudo-random number sequence generation to generate multi-dimensional fields of pseudo-random sequences. The noise coding processor is particularly suited for use in pattern recognition applications and accepts signals representing feature correlations as inputs and derives a pattern to test the feature coherence therefrom.

US Patent:

58122923, Sep 22, 1998

Filed:

Nov 27, 1995

Appl. No.:

8/562920

Inventors:

Joseph P. Garcia - Greenbelt MD

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

G03H 126
H04J 1408

US Classification:

359140

Abstract:

An optical correlator is disclosed that compares signals of interest with lected reference signals stored in holograms. The holograms are arranged so that the selected reference signals impinge onto the plane of the entrance of fiber optics arranged with an optical delay line and fiber optic amplifiers to form a delay line amplifier array. The optical delay line receives the signals of interest represented by light modulated pulses. The cooperative action from the light from the hologram and the light from the optical delay line produces signals that are proportional to the correspondence between the signals of interest and the stored reference signals.

US Patent:

52334406, Aug 3, 1993

Filed:

Jul 16, 1990

Appl. No.:

7/553058

Inventors:

Joseph P. Garcia - Silver Spring MD

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H04N 140
H04N 104

US Classification:

358448

Abstract:

Optical imaging data sampled through a sensing array of spaced receiving faces of optic fiber bundles, is encoded by the different signal delay lengths of the fibers forming the respective bundles. The geometry of such end faces in the array is such as to effect encoding in dependence on the angular orientation and position of sampled segments of the optical data relative to the end faces on which such sampled segments impinge.

US Patent:

57149011, Feb 3, 1998

Filed:

Jul 19, 1995

Appl. No.:

8/504342

Inventors:

Joseph P. Garcia - Greenbelt MD

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H03L 500

US Classification:

327333

Abstract:

An interconnecting network comprising operational amplifiers, summing ampiers, and hysteretic coupling circuits is disclosed. The interconnecting network responds to signals of interest that may be substantially simultaneously present, but only to the highest initial intensity thereof so as to provide priority decoding of signals of interest. The hysteretic coupling circuit has a selectable coupling rate and a selectable coupling constant that allows the hysteretic circuit to respond in a stable so called "winner-take-all" manner, or conversely in a non-stable chaotic manner.

US Patent:

56686536, Sep 16, 1997

Filed:

Jul 19, 1995

Appl. No.:

8/504196

Inventors:

Joseph P. Garcia - Greenbelt MD

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H04J 1408
H04Q 1104

US Classification:

359140

Abstract:

A switching arrangement is disclosed that interconnects a plurality of prssors forming a multi-processor computer system. The switching arrangement comprises optical delay lines that cooperate with microwave switching devices to, provide high speed switching of data packets of the multi-processor computer system. The optical delay lines temporarily store data packets for a sufficient time to allow for the contention resolution circuit to establish priority for any of the data packets that may be competing for a single source. The switching arrangement allows for the servicing of the data packets within a maximum of a few cycles of the clock rate of the computer system and a minimum of less than one clock cycle.