Joseph John Gray

US Patent:

20020120526, Aug 29, 2002

Filed:

Jun 28, 2001

Appl. No.:

09/896070

Inventors:

Donna Albertson - Lafayette CA, US
Daniel Pinkel - Walnut Creek CA, US
Colin Collins - San Rafael CA, US
Joseph Gray - San Francisco CA, US

International Classification:

G06F017/60

US Classification:

705/026000

Abstract:

This invention pertains to the field of cancer genetics and cytogenetics. In particular, this invention pertains to the identification of a novel amplicon on human chromosome 20 which is associated with cancer. More particularly this invention pertains to the identification of a novel “amplicon” or genomic nucleic acid in a region of amplification at about 20q13.2 which has been associated with a variety of cancers, particularly breast cancer. The novel amplicon of the invention can be used as a probe specific for this region of 20q13.2 as well as for the diagnosis and prognosis of various cancers. Also provided are kits for screening for the presence and copy number of the novel amplicon of the invention in a sample containing human nucleic acid

US Patent:

20050196498, Sep 8, 2005

Filed:

Mar 3, 2005

Appl. No.:

11/072138

Inventors:

Joseph Gray - Oakland CA, US

International Classification:

A23L001/00
A23B007/16

US Classification:

426383000

Abstract:

A method for forming an apple into a figure is disclosed. The method comprises peeling and shaping the apple utilizing a blade tool and a scraper tool; cutting outlines into the peeled and shaped apple, and punching out eye holes in the apple utilizing a hole punch. The method further comprises inserting teeth into the apple utilizing a tweezer; and allowing the apple to dry out over a predetermined time period.

US Patent:

58809732, Mar 9, 1999

Filed:

Nov 20, 1996

Appl. No.:

8/752154

Inventors:

Joseph Harold Gray - Palo Alto CA
Lars Morten Jorgensen - San Jose CA

Assignee:

Graychip Inc. - Palo Alto CA

International Classification:

G06F 738

US Classification:

364572

Abstract:

A signal processing system and method for stabilizing cascaded integrator-comb (CIC) interpolation filters. The signal processing system includes an overflow detection circuit and reset circuitry. The overflow detection circuit monitors the output of the CIC interpolation filter for an overflow condition which is indicative of filter instability. When an overflow condition is detected, the reset circuitry automatically resets the filter, thereby eliminating the instability.

US Patent:

46023500, Jul 22, 1986

Filed:

Sep 16, 1985

Appl. No.:

6/776198

Inventors:

Joseph H. Gray - Berkeley CA

Assignee:

TRW Inc. - Redondo Beach CA

International Classification:

G06F 700

US Classification:

364900

Abstract:

A data reordering memory for writing data into the memory in one order and reading data out of the memory in a different order. The data reordering facilitates the processing of the data by a prime factor discrete Fourier transform processor.

US Patent:

46047212, Aug 5, 1986

Filed:

Feb 27, 1985

Appl. No.:

6/706222

Inventors:

Joseph H. Gray - Berkeley CA

Assignee:

TRW Inc. - Redondo Beach CA

International Classification:

G06F 15332

US Classification:

364726

Abstract:

A special purpose computer and method of computation for performing an N-length discrete Fourier transform (DFT) using a sum and difference conjugate prime factor transform. The transform length N is selected as equal to the product of L mutually prime factors N. sub. 1, N. sub. 2,. . . , N. sub. 1,. . . , N. sub. L. For each one of the L mutually prime factors N. sub. i, an N. sub. i -length DFT is performed. Each N. sub. i -length DFT transform is performed using a data processing element called a kernel. Each kernel includes one or more memory elements for reordering data and a computational element. The computational element includes adder circuit means for forming the sum term, SUM(n). sub. i equal to the quantity x(n. sub. i)+x(N. sub. i -n. sub. i) and the difference term, DIFF(n. sub.

US Patent:

48687766, Sep 19, 1989

Filed:

Sep 14, 1987

Appl. No.:

7/059097

Inventors:

Joseph H. Gray - Palo Alto CA
Mark R. Greenstreet - Princeton NJ
Lars M. Jorgensen - San Jose CA

Assignee:

TRW Inc. - Redondo Beach CA

International Classification:

G06F 15332

US Classification:

364726

Abstract:

A fast Fourier transform circuit, including an illustrative radix-eight discrete Fourier transform (DFT) kernel that operates on an n-bit-serial data format, for an efficient serial-like, pipelined operation within the DFT. The circuit performs a four-point DFT on half of the input data words at a time, stores intermediate results from the four-point DFT in a commutation stage, then combines the intermediate results in two two-point DFTs. Internal multiplication in the eight-point DFT is effected in delay registers that also serve to store the intermediate results, thereby providing an economy of timing and circuit routing. Interleaving and deinterleaving operations convert the data format between three-bit-serial and conventional bit-parallel used outside the eight-point DFT kernel, which may therefore be easily cascaded for more complex FFT operations. The DFT kernel also includes means for selectively bypassing butterfly computation modules to perform shorter-length DFTs.

US Patent:

45876266, May 6, 1986

Filed:

Feb 14, 1985

Appl. No.:

6/701830

Inventors:

Joseph H. Gray - Berkeley CA

Assignee:

TRW Inc. - Redondo Beach CA

International Classification:

G06F 15332

US Classification:

364726

Abstract:

A special purpose computer and method of computation for performing an N-length discrete Fourier transform (DFT) using a sum and difference conjugate prime factor transform. The transform length N is selected as equal to the product of L mutually prime factors N. sub. 1, N. sub. 2,. . . , N. sub. i,. . . , N. sub. L. For each one of the L mutually prime factors N. sub. i, an N. sub. i -length DFT is performed. Each N. sub. i -length DFT transform is performed using a data processing element called a kernel. Each kernel includes one or more memory elements for reordering data and a computational element. The computational element includes adder circuit means for forming the sum term, SUM(n. sub. i) equal to the quantity x(n. sub. i)+x(N. sub. i -n. sub. i) and the difference term, DIFF(n. sub.

US Patent:

20230078630, Mar 16, 2023

Filed:

Sep 20, 2022

Appl. No.:

17/948594

Inventors:

- San Ramon CA, US
Michael John Price - Palo Alto CA, US
Joseph Gray - Lafayette CA, US

International Classification:

H04W 4/38
G01M 5/00
G06F 3/023
H04W 4/029
G01S 19/13

Abstract:

Example systems are described for remotely interacting with a portable field measurement device. Systems can include a controller that can: couple to a mobile device; receive user input from a user through the mobile device; cause the portable field measurement device to execute the operations directed by the user; electronically record data output from the portable field measurement device resulting from the directed operations; and report the data to the user via the mobile device, and/or to a remote electronic database. In some embodiments, a robotic arm can be used to actuate the portable field measurement device.