Joseph M Hess

US Patent:

20170256501, Sep 7, 2017

Filed:

Mar 7, 2016

Appl. No.:

15/062452

Inventors:

- Boise ID, US
Joseph L. Hess - Meridian ID, US
Keith E. Ypma - Boise ID, US
Kurt J. Bossart - Eagle ID, US

International Classification:

H01L 23/544
G06T 11/20
H01L 21/66
H01L 25/065
H01L 21/67
H01L 21/68
H01L 25/00
G06T 7/00
H01L 23/48

Abstract:

A method of determining a lateral misregistration between levels of a semiconductor structure comprises imaging at least one first alignment mark in a first level of the structure and at least one second alignment mark in a second level of the structure. A digital image of the first and second alignment marks is formed, each of which are defined by a set of points having an x-value and a y-value. The x-values and y-values of points defining the first alignment mark and points defining the second alignment mark are averaged to determine a center of the first alignment mark and a center of the second alignment mark. An x-coordinate and a y-coordinate of the center of the first alignment mark is subtracted from the respective x-coordinate and y-coordinate of the center of the second alignment mark to determine a lateral misregistration between the first level and the second level. Related methods of forming a semiconductor wafer, semiconductor assembles and metrology tools for use in implementing the methods are disclosed.