1441 Florida Ave, Modesto, CA 95350 2095781211 (Phone)
Modesto Radiological Medical Grp 1524 Mchenry Ave Suite 430, Modesto, CA 95350 2095774444 (Phone)
Certifications:
Diagnostic Radiology, 1993
Awards:
Healthgrades Honor Roll
Languages:
English Spanish
Hospitals:
1441 Florida Ave, Modesto, CA 95350
Modesto Radiological Medical Grp 1524 Mchenry Ave Suite 430, Modesto, CA 95350
Doctors Medical Center - San Pablo 2000 Vale Road, San Pablo, CA 94806
Emanuel Medical Center 825 Delbon Avenue, Turlock, CA 95382
Oak Valley Hospital 350 South Oak Avenue, Oakdale, CA 95361
Education:
Medical School University Of California, San Diego, School Of Medicine Graduated: 1988 Medical School St Marys Hospital Graduated: 1989 Medical School Stanford University Graduated: 1993 Medical School Uc San Francisco Genl Hospital Graduated: 1994
Modesto Radiological Med GrpModesto Radiology Imaging Inc 1524 Mchenry Ave STE 100, Modesto, CA 95350 2095774444 (phone), 2095272069 (fax)
Education:
Medical School University of California, San Diego School of Medicine Graduated: 1988
Languages:
English Spanish
Description:
Dr. Higgins graduated from the University of California, San Diego School of Medicine in 1988. He works in Modesto, CA and specializes in Diagnostic Radiology and Radiology. Dr. Higgins is affiliated with Emanuel Medical Center and Oak Valley Hospital.
1524 Mchenry Ave, Modesto, CA 95350 101 Park Ave, Modesto, CA 95354
Education:
University of California San Diego, School of Medicine - Doctor of Medicine University of California San Diego - Doctor of Philosophy Stanford Hospital & Clinics - Residency - Radiology
Board certifications:
American Board of Radiology Certification in Diagnostic Radiology (Radiology)
Us Patents
Method For Determining The Functional Equivalence Between Two Circuit Models In A Distributed Computing Environment
This invention determines whether two logic level circuit models have equivalent functionality. The method allows difficult portions of the equivalent functionality check to be partitioned and concurrently solved in a distributed computing environment. This permits the user to use, in a scalable fashion, additional computing resources to rapidly solve difficult equivalent functionality checks. The method allows difficult checks to be solved using ( ) a divide-and-conquer approach, ( ) by a competitive approach in which many independent attempts are made to solve the same check, or ( ) by allocating more resources to solve the difficult check.
Method For Rapidly Determining The Functional Equivalence Between Two Circuit Models
Joseph E. Higgins - Albany CA, US Vigyan Singhal - Fremont CA, US Adnan Aziz - Austin TX, US
Assignee:
Tempus Fugit, Inc. - Albany CA
International Classification:
G06F 17/50
US Classification:
716 3, 716 2
Abstract:
This invention determines whether two circuit models have equivalent functionality. The method allows very fast comparison between two circuits taking advantage of previous work done. Whenever an apparatus associated with the method solves a problem, it stores information that learned during the solution of the problem, in a database. If the apparatus is presented with a new problem of determining equivalence between two portions of two circuits, it checks if it has seen sub-circuits similar to either of the two pieces before. If it has, it uses the knowledge cached during the previous checks to make the new check easier. Checking equivalence of two circuit models involves checking equivalence of many pairs of sub-parts. Even when the subsequent comparisons involve different circuits, it is possible to take advantage of the information acquired during previous equivalence checks.
Method For Verifying Properties Of A Circuit Model
Vigyan Singhal - Fremont CA, US Joseph E. Higgins - Albany CA, US
Assignee:
Jasper Design Automation, Inc. - Mountain View CA
International Classification:
G06F 17/50
US Classification:
716 4, 716 5, 716 6
Abstract:
Methodology for verifying properties of a circuit model in context of given environmental constraints is disclosed. Verification of a specified property is performed by analyzing only a portion of the circuit model. The present methodology is also directed towards reducing the computation time for verifying the specified property. Further, the present methodology allows the connection of an additional circuit model to the circuit model in a non-intrusive manner. The connection is made without making any modifications to the description of the circuit model. This permits the straightforward specification of related environmental constraints and properties, which makes it possible to verify correct behavior of complex interfaces.
System And Method For Guiding And Optimizing Formal Verification For A Circuit Design
Vigyan Singhal - Fremont CA, US Joseph E. Higgins - Albany CA, US Chung-Wah Norris Ip - Fremont CA, US Howard Wong-Toi - Albany CA, US
Assignee:
Jasper Design Automation, Inc. - Mountain view CA
International Classification:
G06F 17/50
US Classification:
716 5, 716 4
Abstract:
The present invention is used for guiding formal verification of a circuit design in circuit simulation software to optimize the time required for verification of a circuit design. The invention modifies the analysis region being used for verification in order to optimize the time for verification. The invention allows for manual, semi-automatic, and automatic modification of the analysis region. The modification is done by either expanding or reducing the analysis region or by adding new rules as assumptions to the existing analysis region. The invention also uses the concept of an articulation point for modification of the analysis region. The modification of the analysis region is performed in a manner to optimize time and memory required for verification of the circuit design.
Vigyan Singhal - Fremont CA, US Joseph E. Higgins - Albany CA, US Alok N. Singh - Milipitas CA, US
Assignee:
Jasper Design Automation, Inc. - Mountain Veiw CA
International Classification:
G06F 17/50
US Classification:
716 1, 716 4, 716 5, 716 6
Abstract:
A highlighting system for use with electronic circuit design tools is provided for displaying signal waveforms and Register Transfer Logic (RTL) source code portions corresponding to a selected signal in the same window. The user selects a time and signal to be explored. Based on the selected time and signal, the values of all related signals are identified from a database generated by simulation of RTL source code. Nodes corresponding to the related signals are identified from a gate-level netlist corresponding to the RTL source code and the nodes responsible for the particular value of the selected signal at selected time are identified. The nodes are then mapped on to the RTL source code portions by a process of Instrumentation. The RTL source code portions so identified are then displayed. In particular, the portions of the RTL source code responsible for the particular value or transition in particular value of the signal at the selected time are highlighted.
Name / Title
Company / Classification
Phones & Addresses
Joseph E. Higgins Principle
Tempus Fugit, Inc. Electronic Connectors
525 Curtis Street, Berkeley, CA 94706
Joseph Higgins President
HIGGINS, HIGGINS AND A. V. R. INSURANCE AGENCY, INC
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