Joseph J Link

US Patent:

6687980, Feb 10, 2004

Filed:

Aug 11, 2000

Appl. No.:

09/636664

Inventors:

Joseph Link - Pleasanton CA
Kurt Raab - San Jose CA

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

B23P 1900

US Classification:

29760, 29827, 292811, 292815, 361736

Abstract:

An apparatus for processing flexible tape for microelectronic assemblies includes a base having a top surface, a bottom surface and an aperture extending between the top and bottom surfaces, and a platform having a top surface for engaging a flexible tape used for making microelectronic assemblies, such as semiconductor chip packages. The platform is sized to fit within the aperture extending between the top and bottom surfaces of the base. The base is pivotally secured at one end of the platform so that when the base pivots with respect to the platform, the flexible tape engaged by the platform remains on the platform. The assembly also includes a carrier frame having a slot and a clamp sized to pass through the slot and the carrier frame and the aperture in the base for securing the flexible tape to the top surface of the platform as the base pivots with respect to the platform.

US Patent:

6709469, Mar 23, 2004

Filed:

Aug 30, 2000

Appl. No.:

09/650834

Inventors:

Joseph Link - Pleasanton CA

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H01L 2100

US Classification:

29 2501

Abstract:

A stencil assembly for placing conductive elements over conductive pads accessible at a first surface of a microelectronic element includes a main body having a top surface and a bottom surface and a plurality of openings extending between the top and bottom surfaces, the main body being adapted for overlying the first surface of the microelectronic element so that the openings are in substantial alignment with the pads of the microelectronic element. The stencil assembly also includes a spacer element under the bottom surface of the main body, the spacer element being adapted for maintaining the main body above the first surface of the microelectronic element and remote from the pads of the microelectronic element. The main body and the spacer element have a combined thickness that is substantially equivalent to the diameter of the conductive elements.

US Patent:

44411197, Apr 3, 1984

Filed:

Jan 15, 1981

Appl. No.:

6/273848

Inventors:

Joseph Link - Carrollton TX

Assignee:

Mostek Corporation - Carrollton TX

International Classification:

H01L 2302
H01L 3902
H02G 1308

US Classification:

357 74

Abstract:

An improved integrated circuit package (10) includes a cover (12), an intermediate subassembly (14) and a bottom subassembly (16). The intermediate and bottom subassemblies (14, 16) include lead frames (48, 22) respectively embedded therein, as well as openings which define a cavity for a semiconductor chip. The external lead pins (24) of the bottom subassembly (16) permit interconnection of the package with a circuit board or the like, while the external contacts (50) of the intermediate subassembly (14) cooperate with openings (62) in the cover to provide integral socket connections for other semiconductor packages or electrical components.

US Patent:

61626619, Dec 19, 2000

Filed:

May 29, 1998

Appl. No.:

9/086808

Inventors:

Joseph Link - Pleasanton CA

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

H01L 2144
H01L 2148
H01L 2150

US Classification:

438108

Abstract:

A method placing conductive elements, such as solder balls, over terminals on a microelectronic assembly includes providing a microelectronic element having a first surface and one or more terminals accessible at the first surface, and securing a spacer plate having a top surface, a bottom surface and at least one opening extending therethrough over the first surface of the microelectronic element so that the at least one opening is in substantial alignment with the terminals. After the spacer plate has been secured over the first surface of the microelectronic element, a stencil for placing conductive elements is then secured over the spacer plate. The stencil has a top surface and a bottom surface and a plurality of openings extending therethrough. When the stencil is secured over the spacer plate, the plurality of openings in the stencil are in substantial alignment with the terminals. As a result, the spacer plate maintains the stencil remote from the terminals.

US Patent:

50557041, Oct 8, 1991

Filed:

Aug 4, 1989

Appl. No.:

7/389538

Inventors:

Joseph Link - Carrollton TX
Michael L. Bolan - Dallas TX
Allen H. Brunk - Carrollton TX
Paul E. Schneikart - Lewisville TX

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

H02J 900
H01L 23495

US Classification:

307 66

Abstract:

An integrated circuit, typically a random access memory, is housed in a package (14). In the application associated with the integrated circuit it is desired to maintain the data states stored in the memory even when the normal supply voltage is disconnected from the package (14). Batteries (24, 26) are secured in recesses (20, 22) within a structure (12) which is connected to the integrated circuit package (14). A top spring clip (100) is provided to securely hold the batteries (24, 26) within the recesses (20, 22) and forms a common conductor in contact with the upper terminal of both batteries. A bottom spring clip (74, 76) is provided for each of the recesses (20, 22) to form separate conductors in contact with the lower terminal of each battery. The batteries can be readily inserted and removed over lips (64, 70) in the recess (20, 22).

US Patent:

43420699, Jul 27, 1982

Filed:

Feb 13, 1981

Appl. No.:

6/234400

Inventors:

Joseph Link - Carrollton TX

Assignee:

Mostek Corporation - Carrollton TX

International Classification:

H05K 114

US Classification:

361401

Abstract:

An integrated semiconductor package containing circuitry capable of supporting separately packaged semiconductors to achieve greater circuit board density and to allow separate semiconductor packages which cooperate with the supporting semiconductor package and die to be interchanged. The supporting die is interconnected electrically to lead pins and socket contacts using conductive circuitry compatible with the other semiconductor die. In a first embodiment corresponding metallization patterns are used to electrically interconnect an integrated circuit package to a conventional printed wiring board or ceramic wiring board containing socket contacts to receive lead pins from another integrated circuit package. A second embodiment is a unitized package containing integral socket contacts within the unitized integrated package to receive lead pins from another integrated circuit package.

US Patent:

61701513, Jan 9, 2001

Filed:

Nov 19, 1999

Appl. No.:

9/443530

Inventors:

Joseph Link - Pleasanton CA
Kurt Raab - San Jose CA

Assignee:

Tessera, Inc. - San Jose CA

International Classification:

B23P 1904

US Classification:

29740

Abstract:

An assembly for processing a flexible tape comprises a carrier frame having a slot and a cut-out region contiguous with one end of the slot for selectively transferring the flexible tape from the top surface of the carrier frame to the bottom surface of the carrier frame. An apparatus for processing the flexible tape is also disclosed and includes the carrier frame, a base having an aperture and a platform sized to fit within the aperture of the base. The base is pivotable around one end of the platform.

US Patent:

52763544, Jan 4, 1994

Filed:

Mar 25, 1991

Appl. No.:

7/675074

Inventors:

Joseph Link - Carrollton TX
Michael L. Bolan - Dallas TX
Allen H. Brunk - Carrollton TX
Paul E. Schneikart - Lewisville TX

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

H02J 900
H01L 2348

US Classification:

307 66

Abstract:

An integrated circuit, typically a random access memory, is housed in a package (14). In the application associated with the integrated circuit it is desired to maintain the data states stored in the memory even when the normal supply voltage is disconnected from the package (14). Batteries (24, 26) are secured in recesses (20, 22) within a structure (12) which is connected to the integrated circuit package (14). A top spring clip (100) is provided to securely hold the batteries (24, 26) within the recesses (20, 22) and forms a common conductor in contact with the upper terminal of both batteries. A bottom spring clip (74, 76) is provided for each of the recesses (20, 22) to form separate conductors in contact with the lower terminal of each battery. The batteries can be readily inserted and removed over lips (64, 70) in the recess (20, 22).