Joseph C Marshall

US Patent:

6996443, Feb 7, 2006

Filed:

Dec 31, 2002

Appl. No.:

10/334317

Inventors:

Joseph R. Marshall - Manassas VA, US
Alan F. Dennis - Chantilly VA, US
Charles A. Dennis - Warrenton VA, US
Steven G. Santee - Bristow VA, US

Assignee:

Bae Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

G06N 5/00

US Classification:

700 87, 712 1

Abstract:

A reconfigurable digital processing system for space includes the utilization of field programmable gate arrays utilizing a hardware centric approach to reconfigure software processors in a space vehicle through the reprogramming of multiple FPGAs such that one obtains a power/performance characteristic for signal processing tasks that cannot be achieved simply through the use of off-the-shelf processors. In one embodiment, for damaged or otherwise inoperable signal processors located on a spacecraft, the remaining processors which are undamaged can be reconfigured through changing the machine language and binary to the field programmable gate arrays to change the core processor while at the same time maintaining undamaged components so that the signal processing functions can be restored utilizing a RAM-based FPGA as a signal processor. In one embodiment, multiple FPGAs are connected together by a data bus and are also provided with data pipes which interconnect selected FPGAs together to provide the necessary processing function. Flexibility in reconfiguration includes the utilizing of a timing and synchronization block as well as a common configuration block which when coupled to an interconnect block permits reconfiguration of a customizable application core, depending on the particular signal processing function desired.

US Patent:

7142953, Nov 28, 2006

Filed:

Sep 25, 2003

Appl. No.:

10/672844

Inventors:

Joseph R. Marshall - Manassas VA, US
Alan F. Dennis - Chantilly VA, US
Charles A. Dennis - Warrenton VA, US
Steven G. Santee - Bristow VA, US

Assignee:

Bae Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

B64C 1/36

US Classification:

701 13, 701 9, 701 33, 712 1

Abstract:

A reconfigurable digital processing system for space includes the utilization of field programmable gate arrays utilizing a hardware centric approach to reconfigure software processors in a space vehicle through the reprogramming of multiple FPGAs such that one obtains a power/performance characteristic for signal processing tasks that cannot be achieved simply through the use of off-the-shelf processors. In one embodiment, for damaged or otherwise inoperable signal processors located on a spacecraft, the remaining processors which are undamaged can be reconfigured through changing the machine language and binary to the field programmable gate arrays to change the core processor while at the same time maintaining undamaged components so that the signal processing functions can be restored utilizing a RAM-based FPGA as a signal processor. In one embodiment, multiple FPGAs are connected together by a data bus and are also provided with data pipes which interconnect selected FPGAs together to provide the necessary processing function. Flexibility in reconfiguration includes the utilizing of a timing and synchronization block as well as a common configuration block which when coupled to an interconnect block permits reconfiguration of a customizable application core, depending on the particular signal processing function desired.

US Patent:

7337160, Feb 26, 2008

Filed:

Aug 12, 2004

Appl. No.:

10/918814

Inventors:

Joseph R. Marshall - Manassas VA, US
Richard W. Berger - Woodbridge VA, US
John C. Rodgers - Fairfax VA, US

Assignee:

BAE Systems Information and Electronic Systems Integration Inc. - Nashua NH

International Classification:

G06N 5/00

US Classification:

706 62, 706 45

Abstract:

Chalcogenide technology is used for radiation hardening for spaceborne systems and more particularly in C-RAM form for processors, field programmable gate arrays, startup RAMs, shadow storage and single-chip systems to protect these units.

US Patent:

60651350, May 16, 2000

Filed:

Jun 4, 1999

Appl. No.:

9/325641

Inventors:

Joseph R. Marshall - Manassas VA
Dale G. Langston - Manassas VA

Assignee:

Lockhead Martin Corporation - Bethesda MD

International Classification:

G06F 1100

US Classification:

714 11

Abstract:

A lockstep processor system adds error detection, isolation, and recovery logic to one or more lockstep processor system functions; namely, control outputs, processor inputs, I/O busses, memory address busses, and memory data busses.

US Patent:

59150823, Jun 22, 1999

Filed:

Jun 7, 1996

Appl. No.:

8/660640

Inventors:

Joseph R. Marshall - Manassas VA
Dale G. Langston - Manassas VA

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

G06F 1108

US Classification:

39518209

Abstract:

A lockstep processor system adds error detection, isolation, and recovery logic to one or more lockstep processor system functions; namely, control outputs, processor inputs, I/O busses, memory address busses, and memory data busses.