Joseph C Mathis

US Patent:

54448549, Aug 22, 1995

Filed:

Mar 6, 1992

Appl. No.:

7/849643

Inventors:

Joseph R. Mathis - Georgetown TX
Richard R. Oehler - Somers NY
Carl Zeitler - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

395825

Abstract:

A data processing system including a processor that issues communications commands on a first communications channel and a peripheral device that is connected to the first communications channel and to a second communications channel that operates asynchronously relative to the first communications channel. The peripheral device performs communications operations specified from the commands from the processor and further responds to communications over the second communications channel. The peripheral device includes a controller that provides a status word to the processor in response to the command issued to the peripheral device. The status word indicates the status condition of the peripheral device at the time when the peripheral device initiates the operation specified by the issued command.

US Patent:

52513033, Oct 5, 1993

Filed:

Jan 13, 1989

Appl. No.:

7/297778

Inventors:

Richard G. Fogg - Austin TX
Joseph R. Mathis - Georgetown TX
James O. Nicholson - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1328

US Classification:

395275

Abstract:

A DMA controller has an attached, dedicated memory. Data objects are stored on the heap and connected by pointers. Each data object contains DMA block transfer control parameters. A single block transfer made up of several separate transfers, with each separate transfer defined by one data object. The single block transfer is defined by linking several data objects into a list. The DMA controller consecutively performs the transfers in a linked list without requiring control by a system central processor.

US Patent:

49950568, Feb 19, 1991

Filed:

Jan 13, 1989

Appl. No.:

7/297776

Inventors:

Richard G. Fogg - Austin TX
Joseph R. Mathis - Georgetown TX
Carl Zeitler - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04B 138

US Classification:

375 7

Abstract:

In a communications system, a sending system and a receiving system have multiple data buffers. In response to an inquiry from the sending system, the receiving system transmits information which indicates the size and number of data buffers available in the receiving system. The sending system then begins transmitting data frames, which are placed into the buffers of the receiving system. When the receiving system removes all of the data from a buffer, therefore freeing it to accept additional data, it sends a signal to the sending system indicating this fact. The sending system counts such signals, and ensures that the number of transmitted data frames does not exceed the number of frames which have been removed from the receiver's buffers by more than the number of buffers which the receiver has.

US Patent:

50540190, Oct 1, 1991

Filed:

Jan 13, 1989

Appl. No.:

7/297777

Inventors:

Joseph R. Mathis - Georgetown TX
Gerald L. Rouse - Round Rock TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04B 320
H04L 516

US Classification:

370 31

Abstract:

In a network communications system, data is transferred from a first node to a second node. When requested, the second node can transmit a data direction turnaround message to the first node, followed by transferring data to the first node. Data transfer in both directions is made during a single communications link within the network. The turnaround message can function as an acknowledgement of successful transfer to the data transferred from the first node to the second node.