Joseph H Murray

US Patent:

6567871, May 20, 2003

Filed:

Jul 26, 1999

Appl. No.:

09/361367

Inventors:

Lee K. Koh - Tempe AZ
Joseph Murray - Scottsdale AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

710110, 710310

Abstract:

A method and apparatus is described that is related to repeating (extending) transactions on a bus. A plurality of buffer pairs are configured to direct a plurality of signals between a first bus and a second bus in a bus cycle. A circuit is configured to monitor a control signal to determine a bus location of a master device and the circuit is further configured to enable one buffer in the buffer pairs to control a direction of the plurality of signals between the first bus and the second bus.

US Patent:

6577174, Jun 10, 2003

Filed:

Jul 23, 2001

Appl. No.:

09/910999

Inventors:

Kevin Wayne Locker - Scottsdale AZ
Joseph Murray - Scottsdale AZ

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H03L 700

US Classification:

327141, 327144

Abstract:

Symmetrical cross coupled PLL circuits provide pseudo-synchronization between two independent clock signals, especially for use in fault tolerant applications. Independent oscillators provide input signals to each of the PLL circuits. The PLL circuits include divide circuitry that provide output signals at some sub multiple of the input clock signals. The phase relationship between the output clock signals from the cross coupled PLL circuits is monitored by phase detector circuits. If the phase of one output clock signal is determined to be advanced relative to the other output clock signal, the phase of that output clock signal is retarded by temporarily increasing the divide ratio of the PLL circuit producing the phase advanced signal.

US Patent:

7124230, Oct 17, 2006

Filed:

Apr 30, 2002

Appl. No.:

10/136660

Inventors:

David Russell Smith - Phoenix AZ, US
Richard Paul Mackey - Phoenix AZ, US
Joseph Murray - Scottsdale AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/36
G06F 13/372
G06F 13/00

US Classification:

710310, 710306, 710129, 710301

Abstract:

A peripheral component interconnect-extended system that includes a bus bridge. The bus bridge includes an input queue adapted to receive a first request for data from a requesting device coupled to a first bus. The first bus is coupled to the bus bridge, and the first request containing a sequence identification information. The bus bridge also includes a data storage device to contain information to control the bus bridge, and a processor that associates a first unique identification code to the first request.

US Patent:

20040128464, Jul 1, 2004

Filed:

Dec 30, 2002

Appl. No.:

10/331843

Inventors:

Micheil Lee - Tempe AZ, US
Richard MacKey - Phoenix AZ, US
Joseph Murray - Scottsdale AZ, US
Marc Goldschmidt - Scottsdale AZ, US
Mark Schmisseur - Phoenix AZ, US

International Classification:

G06F012/00
G11C011/34
G11C016/06

US Classification:

711/171000, 365/185090, 365/185110

Abstract:

Embodiments of the present invention provide for configurable memory bus width and memory reclamation. In particular, the memory controller is configured to use a width of memory that is less than that fully available such that back-to-back writes can occur, as opposed to read-modify-writes. Unused regions of memory (defined by the total available memory width subtracted by the managed memory width) are partially or fully reclaimed, thus increasing the effective memory size available to the user. The configuration methods accommodate multiple interface bus widths while maintaining bandwidth not previously possible.

US Patent:

20040128465, Jul 1, 2004

Filed:

Dec 30, 2002

Appl. No.:

10/331860

Inventors:

Micheil Lee - Tempe AZ, US
Richard Mackey - Phoenix AZ, US
Joseph Murray - Scottsdale AZ, US
Marc Goldschmidt - Scottsdale AZ, US
Mark Schmisseur - Phoenix AZ, US

International Classification:

G06F012/00

US Classification:

711/171000, 711/172000

Abstract:

A method and apparatus for providing a configurable memory data width including a device supporting a first data width, a memory supporting a second data width, and a controller. The controller configures a first sub-region of memory having a data width less than that fully available when the data width supported by the device differs from the data width supported by the region of memory, and maps data from the device to the configured first sub-region of the memory. The controller implements a constant in an unused region of the memory, and calculates error correction data based upon the data mapped in the sub-region of the memory and the constant value in the unused region of the memory.

US Patent:

20050289253, Dec 29, 2005

Filed:

Jun 24, 2004

Appl. No.:

10/877587

Inventors:

Samantha Edirisooriya - Tempe AZ, US
Joseph Murray - Scottsdale AZ, US
Gregory Tse - Tempe AZ, US
Vishram Sarurkar - Bangalore, IN
Manish Goel - Bangalore, IN

International Classification:

G06F013/28

US Classification:

710022000

Abstract:

A method and apparatus for a multi-function direct memory access core are described. In one embodiment, the method includes the reading of a direct memory access (DMA) descriptor having associated DMA data to identify at least one micro-command. Once the micro-command is identified, the DMA data is processed according to the micro-command during DMA transfer of the data. In one embodiment, a DMA engine performs an operation on the DMA data in transit within the DMA controller according to the identified micro-command. Hence, by defining a primitive set of micro-commands, the DMA engine within, for example, an input/output (I/O) controller hub (ICH), can be used to perform a large number of complex operations on data when data is passing through the ICH without introducing latency into the DMA transfer. Other embodiments are described and claimed.

US Patent:

20060047934, Mar 2, 2006

Filed:

Aug 31, 2004

Appl. No.:

10/931278

Inventors:

Mark Schmisseur - Phoenix AZ, US
Joseph Murray - Scottsdale AZ, US
Richard Mackey - Phoenix AZ, US
Micheil Lee - Phoenix AZ, US

International Classification:

G06F 12/00

US Classification:

711168000

Abstract:

A method according to one embodiment may include selecting a port, among a plurality of ports. The method of this embodiment may also include selecting between a memory read request and a memory write request from at least one port, among the plurality of ports, based on, at least in part, at least one memory access rule. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

US Patent:

20060136619, Jun 22, 2006

Filed:

Dec 16, 2004

Appl. No.:

11/017183

Inventors:

Samantha Edirisooriya - Tempe AZ, US
Gregory Tse - Tempe AZ, US
Joseph Murray - Scottsdale AZ, US

International Classification:

G06F 5/00

US Classification:

710052000

Abstract:

Techniques to accelerate block guard processing of data by use of block guard units in a path between a source memory device and an originator of a data transfer request. The block guard unit may intercept the data transfer request and data transferred in response to the data transfer request. The block guard unit may utilize a cache to store information useful to verify block guards associated with the data.